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	board: fsl: lx2160a: Add support to reset to eMMC
Add support of "qixis_reset emmc" command for lx2160a based platforms Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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						 Priyanka Jain
						Priyanka Jain
					
				
			
			
				
	
			
			
			
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			| @@ -1,6 +1,7 @@ | |||||||
| // SPDX-License-Identifier: GPL-2.0+ | // SPDX-License-Identifier: GPL-2.0+ | ||||||
| /* | /* | ||||||
|  * Copyright 2011 Freescale Semiconductor |  * Copyright 2011 Freescale Semiconductor | ||||||
|  |  * Copyright 2020 NXP | ||||||
|  * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> |  * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> | ||||||
|  * |  * | ||||||
|  * This file provides support for the QIXIS of some Freescale reference boards. |  * This file provides support for the QIXIS of some Freescale reference boards. | ||||||
| @@ -287,7 +288,9 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar | |||||||
| #ifdef QIXIS_LBMAP_EMMC | #ifdef QIXIS_LBMAP_EMMC | ||||||
| 		QIXIS_WRITE(rst_ctl, 0x30); | 		QIXIS_WRITE(rst_ctl, 0x30); | ||||||
| 		QIXIS_WRITE(rcfg_ctl, 0); | 		QIXIS_WRITE(rcfg_ctl, 0); | ||||||
|  | #ifndef NON_EXTENDED_DUTCFG | ||||||
| 		set_lbmap(QIXIS_LBMAP_EMMC); | 		set_lbmap(QIXIS_LBMAP_EMMC); | ||||||
|  | #endif | ||||||
| 		set_rcw_src(QIXIS_RCW_SRC_EMMC); | 		set_rcw_src(QIXIS_RCW_SRC_EMMC); | ||||||
| 		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); | 		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); | ||||||
| 		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); | 		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); | ||||||
| @@ -365,6 +368,7 @@ U_BOOT_CMD( | |||||||
| 	"qixis watchdog <watchdog_period> - set the watchdog period\n" | 	"qixis watchdog <watchdog_period> - set the watchdog period\n" | ||||||
| 	"	period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" | 	"	period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" | ||||||
| 	"qixis_reset dump - display the QIXIS registers\n" | 	"qixis_reset dump - display the QIXIS registers\n" | ||||||
|  | 	"qixis_reset emmc - reset to emmc\n" | ||||||
| 	"qixis_reset switch - display switch\n" | 	"qixis_reset switch - display switch\n" | ||||||
| 	); | 	); | ||||||
| #endif | #endif | ||||||
|   | |||||||
| @@ -306,6 +306,8 @@ int checkboard(void) | |||||||
|  |  | ||||||
| 	if (src == BOOT_SOURCE_SD_MMC) { | 	if (src == BOOT_SOURCE_SD_MMC) { | ||||||
| 		puts("SD\n"); | 		puts("SD\n"); | ||||||
|  | 	} else if (src == BOOT_SOURCE_SD_MMC2) { | ||||||
|  | 		puts("eMMC\n"); | ||||||
| 	} else { | 	} else { | ||||||
| 		sw = QIXIS_READ(brdcfg[0]); | 		sw = QIXIS_READ(brdcfg[0]); | ||||||
| 		sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; | 		sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; | ||||||
|   | |||||||
| @@ -22,7 +22,9 @@ | |||||||
| #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08 | ||||||
| #define QIXIS_LBMAP_MASK		0x0f | #define QIXIS_LBMAP_MASK		0x0f | ||||||
| #define QIXIS_LBMAP_SD | #define QIXIS_LBMAP_SD | ||||||
|  | #define QIXIS_LBMAP_EMMC | ||||||
| #define QIXIS_RCW_SRC_SD		0x08 | #define QIXIS_RCW_SRC_SD		0x08 | ||||||
|  | #define QIXIS_RCW_SRC_EMMC         0x09 | ||||||
| #define NON_EXTENDED_DUTCFG | #define NON_EXTENDED_DUTCFG | ||||||
| #define QIXIS_SDID_MASK			0x07 | #define QIXIS_SDID_MASK			0x07 | ||||||
| #define QIXIS_ESDHC_NO_ADAPTER		0x7 | #define QIXIS_ESDHC_NO_ADAPTER		0x7 | ||||||
|   | |||||||
| @@ -22,7 +22,9 @@ | |||||||
| #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08 | ||||||
| #define QIXIS_LBMAP_MASK		0x0f | #define QIXIS_LBMAP_MASK		0x0f | ||||||
| #define QIXIS_LBMAP_SD | #define QIXIS_LBMAP_SD | ||||||
|  | #define QIXIS_LBMAP_EMMC | ||||||
| #define QIXIS_RCW_SRC_SD           0x08 | #define QIXIS_RCW_SRC_SD           0x08 | ||||||
|  | #define QIXIS_RCW_SRC_EMMC         0x09 | ||||||
| #define NON_EXTENDED_DUTCFG | #define NON_EXTENDED_DUTCFG | ||||||
|  |  | ||||||
| /* VID */ | /* VID */ | ||||||
|   | |||||||
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