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x86: Add DSDT table for supporting ACPI on QEMU
The DSDT table contains a bytecode that is executed by a driver in the kernel. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Tested with QEMU '-M q35' Tested-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Saket Sinha
Simon Glass
@@ -8,5 +8,5 @@ ifndef CONFIG_EFI_STUB
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obj-y += car.o dram.o
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endif
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obj-y += qemu.o
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obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
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obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
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obj-$(CONFIG_PCI) += pci.o
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80
arch/x86/cpu/qemu/acpi/cpu-hotplug.asl
Normal file
80
arch/x86/cpu/qemu/acpi/cpu-hotplug.asl
Normal file
@@ -0,0 +1,80 @@
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/* CPU hotplug */
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Scope(\_SB) {
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/* Objects filled in by run-time generated SSDT */
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External(NTFY, MethodObj)
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External(CPON, PkgObj)
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/* Methods called by run-time generated SSDT Processor objects */
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Method(CPMA, 1, NotSerialized) {
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/*
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* _MAT method - create an madt apic buffer
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* Arg0 = Processor ID = Local APIC ID
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* Local0 = CPON flag for this cpu
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*/
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Store(DerefOf(Index(CPON, Arg0)), Local0)
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/* Local1 = Buffer (in madt apic form) to return */
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Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
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/* Update the processor id, lapic id, and enable/disable status */
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Store(Arg0, Index(Local1, 2))
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Store(Arg0, Index(Local1, 3))
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Store(Local0, Index(Local1, 4))
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Return (Local1)
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}
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Method(CPST, 1, NotSerialized) {
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/*
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* _STA method - return ON status of cpu
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* Arg0 = Processor ID = Local APIC ID
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* Local0 = CPON flag for this cpu
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*/
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Store(DerefOf(Index(CPON, Arg0)), Local0)
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If (Local0) {
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Return (0xf)
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} Else {
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Return (0x0)
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}
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}
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Method(CPEJ, 2, NotSerialized) {
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/* _EJ0 method - eject callback */
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Sleep(200)
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}
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/* CPU hotplug notify method */
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OperationRegion(PRST, SystemIO, 0xaf00, 32)
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Field(PRST, ByteAcc, NoLock, Preserve) {
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PRS, 256
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}
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Method(PRSC, 0) {
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/* Local5 = active cpu bitmap */
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Store(PRS, Local5)
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/* Local2 = last read byte from bitmap */
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Store(Zero, Local2)
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/* Local0 = Processor ID / APIC ID iterator */
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Store(Zero, Local0)
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While (LLess(Local0, SizeOf(CPON))) {
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/* Local1 = CPON flag for this cpu */
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Store(DerefOf(Index(CPON, Local0)), Local1)
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If (And(Local0, 0x07)) {
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/* Shift down previously read bitmap byte */
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ShiftRight(Local2, 1, Local2)
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} Else {
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/* Read next byte from cpu bitmap */
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Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
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}
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/* Local3 = active state for this cpu */
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Store(And(Local2, 1), Local3)
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If (LNotEqual(Local1, Local3)) {
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/* State change - update CPON with new state */
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Store(Local3, Index(CPON, Local0))
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/* Do CPU notify */
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If (LEqual(Local3, 1)) {
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NTFY(Local0, 1)
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} Else {
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NTFY(Local0, 3)
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}
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}
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Increment(Local0)
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}
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}
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}
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25
arch/x86/cpu/qemu/acpi/dbug.asl
Normal file
25
arch/x86/cpu/qemu/acpi/dbug.asl
Normal file
@@ -0,0 +1,25 @@
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/* Debugging */
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Scope(\) {
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/* Debug Output */
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OperationRegion(DBG, SystemIO, 0x0402, 0x01)
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Field(DBG, ByteAcc, NoLock, Preserve) {
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DBGB, 8,
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}
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/*
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* Debug method - use this method to send output to the QEMU
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* BIOS debug port. This method handles strings, integers,
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* and buffers. For example: DBUG("abc") DBUG(0x123)
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*/
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Method(DBUG, 1) {
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ToHexString(Arg0, Local0)
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ToBuffer(Local0, Local0)
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Subtract(SizeOf(Local0), 1, Local1)
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Store(Zero, Local2)
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While (LLess(Local2, Local1)) {
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Store(DerefOf(Index(Local0, Local2)), DBGB)
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Increment(Local2)
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}
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Store(0x0a, dbgb)
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}
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}
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31
arch/x86/cpu/qemu/acpi/hpet.asl
Normal file
31
arch/x86/cpu/qemu/acpi/hpet.asl
Normal file
@@ -0,0 +1,31 @@
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/* HPET */
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Scope(\_SB) {
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Device(HPET) {
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Name(_HID, EISAID("PNP0103"))
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Name(_UID, 0)
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OperationRegion(HPTM, SystemMemory, 0xfed00000, 0x400)
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Field(HPTM, DWordAcc, Lock, Preserve) {
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VEND, 32,
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PRD, 32,
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}
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Method(_STA, 0, NotSerialized) {
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Store(VEND, Local0)
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Store(PRD, Local1)
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ShiftRight(Local0, 16, Local0)
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If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) {
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Return (0x0)
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}
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If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) {
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Return (0x0)
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}
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Return (0x0f)
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}
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Name(_CRS, ResourceTemplate() {
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Memory32Fixed(ReadOnly,
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0xfed00000, /* Address Base */
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0x00000400, /* Address Length */
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)
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})
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}
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}
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102
arch/x86/cpu/qemu/acpi/isa.asl
Normal file
102
arch/x86/cpu/qemu/acpi/isa.asl
Normal file
@@ -0,0 +1,102 @@
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/* Common legacy ISA style devices. */
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Scope(\_SB.PCI0.ISA) {
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Device(RTC) {
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Name(_HID, EisaId("PNP0B00"))
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x0070, 0x0070, 0x10, 0x02)
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IRQNoFlags() { 8 }
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IO(Decode16, 0x0072, 0x0072, 0x02, 0x06)
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})
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}
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Device(KBD) {
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Name(_HID, EisaId("PNP0303"))
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Method(_STA, 0, NotSerialized) {
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Return (0x0f)
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}
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x0060, 0x0060, 0x01, 0x01)
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IO(Decode16, 0x0064, 0x0064, 0x01, 0x01)
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IRQNoFlags() { 1 }
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})
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}
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Device(MOU) {
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Name(_HID, EisaId("PNP0F13"))
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Method(_STA, 0, NotSerialized) {
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Return (0x0f)
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}
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Name(_CRS, ResourceTemplate() {
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IRQNoFlags() { 12 }
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})
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}
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Device(FDC0) {
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Name(_HID, EisaId("PNP0700"))
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Method(_STA, 0, NotSerialized) {
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Store(FDEN, Local0)
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If (LEqual(Local0, 0)) {
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Return (0x00)
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} Else {
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Return (0x0f)
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}
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}
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x03f2, 0x03f2, 0x00, 0x04)
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IO(Decode16, 0x03f7, 0x03f7, 0x00, 0x01)
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IRQNoFlags() { 6 }
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DMA(Compatibility, NotBusMaster, Transfer8) { 2 }
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})
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}
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Device(LPT) {
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Name(_HID, EisaId("PNP0400"))
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Method(_STA, 0, NotSerialized) {
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Store(LPEN, Local0)
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If (LEqual(Local0, 0)) {
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Return (0x00)
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} Else {
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Return (0x0f)
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}
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}
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x0378, 0x0378, 0x08, 0x08)
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IRQNoFlags() { 7 }
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})
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}
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Device(COM1) {
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Name(_HID, EisaId("PNP0501"))
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Name(_UID, 0x01)
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Method(_STA, 0, NotSerialized) {
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Store(CAEN, Local0)
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If (LEqual(Local0, 0)) {
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Return (0x00)
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} Else {
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Return (0x0f)
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}
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}
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x03f8, 0x03f8, 0x00, 0x08)
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IRQNoFlags() { 4 }
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})
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}
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Device(COM2) {
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Name(_HID, EisaId("PNP0501"))
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Name(_UID, 0x02)
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Method(_STA, 0, NotSerialized) {
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Store(CBEN, Local0)
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If (LEqual(Local0, 0)) {
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Return (0x00)
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} Else {
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Return (0x0f)
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}
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}
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Name(_CRS, ResourceTemplate() {
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IO(Decode16, 0x02f8, 0x02f8, 0x00, 0x08)
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IRQNoFlags() { 3 }
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})
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}
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}
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61
arch/x86/cpu/qemu/acpi/pci-crs.asl
Normal file
61
arch/x86/cpu/qemu/acpi/pci-crs.asl
Normal file
@@ -0,0 +1,61 @@
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/* PCI CRS (current resources) definition. */
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Scope(\_SB.PCI0) {
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Name(CRES, ResourceTemplate() {
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WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, /* Address Space Granularity */
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0x0000, /* Address Range Minimum */
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0x00ff, /* Address Range Maximum */
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0x0000, /* Address Translation Offset */
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0x0100, /* Address Length */
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,, )
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IO(Decode16,
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0x0cf8, /* Address Range Minimum */
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0x0cf8, /* Address Range Maximum */
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0x01, /* Address Alignment */
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0x08, /* Address Length */
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)
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, /* Address Space Granularity */
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0x0000, /* Address Range Minimum */
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0x0cf7, /* Address Range Maximum */
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0x0000, /* Address Translation Offset */
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0x0cf8, /* Address Length */
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,, , TypeStatic)
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WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, /* Address Space Granularity */
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0x0d00, /* Address Range Minimum */
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0xffff, /* Address Range Maximum */
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0x0000, /* Address Translation Offset */
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0xf300, /* Address Length */
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,, , TypeStatic)
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, /* Address Space Granularity */
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0x000a0000, /* Address Range Minimum */
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0x000bffff, /* Address Range Maximum */
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0x00000000, /* Address Translation Offset */
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0x00020000, /* Address Length */
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,, , AddressRangeMemory, TypeStatic)
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DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
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0x00000000, /* Address Space Granularity */
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0xe0000000, /* Address Range Minimum */
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0xfebfffff, /* Address Range Maximum */
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0x00000000, /* Address Translation Offset */
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0x1ec00000, /* Address Length */
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,, PW32, AddressRangeMemory, TypeStatic)
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})
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Name(CR64, ResourceTemplate() {
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QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, /* Address Space Granularity */
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0x80000000, /* Address Range Minimum */
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0xffffffff, /* Address Range Maximum */
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0x00000000, /* Address Translation Offset */
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0x80000000, /* Address Length */
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,, PW64, AddressRangeMemory, TypeStatic)
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})
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Method(_CRS, 0) {
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Return (CRES)
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}
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}
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412
arch/x86/cpu/qemu/dsdt.asl
Normal file
412
arch/x86/cpu/qemu/dsdt.asl
Normal file
@@ -0,0 +1,412 @@
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/*
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* QEMU ACPI DSDT ASL definition
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Copyright (c) 2010 Isaku Yamahata
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* yamahata at valinux co jp
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* Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
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*/
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DefinitionBlock (
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"dsdt.aml", /* Output Filename */
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"DSDT", /* Signature */
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0x01, /* DSDT Compliance Revision */
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"UBOO", /* OEMID */
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"UBOOT ", /* TABLE ID */
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0x2 /* OEM Revision */
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)
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{
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#include "acpi/dbug.asl"
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Scope(\_SB) {
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OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
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OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
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Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
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PCIB, 8,
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}
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}
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/* PCI Bus definition */
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Scope(\_SB) {
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Device(PCI0) {
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Name(_HID, EisaId("PNP0A08"))
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Name(_CID, EisaId("PNP0A03"))
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Name(_ADR, 0x00)
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Name(_UID, 1)
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/* _OSC: based on sample of ACPI3.0b spec */
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Name(SUPP, 0) /* PCI _OSC Support Field value */
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Name(CTRL, 0) /* PCI _OSC Control Field value */
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Method(_OSC, 4) {
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/* Create DWORD-addressable fields from Capabilities Buffer */
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CreateDWordField(Arg3, 0, CDW1)
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/* Check for proper UUID */
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If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
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{
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/* Create DWORD-addressable fields from Capabilities Buffer */
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CreateDWordField(Arg3, 4, CDW2)
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CreateDWordField(Arg3, 8, CDW3)
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/* Save Capabilities DWORD2 & 3 */
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Store(CDW2, SUPP)
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Store(CDW3, CTRL)
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/*
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* Always allow native PME, AER (no dependencies)
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* Never allow SHPC (no SHPC controller in this system)
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*/
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And(CTRL, 0x1d, CTRL)
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If (LNotEqual(Arg1, One)) {
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/* Unknown revision */
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Or(CDW1, 0x08, CDW1)
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}
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If (LNotEqual(CDW3, CTRL)) {
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/* Capabilities bits were masked */
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Or(CDW1, 0x10, CDW1)
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}
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/* Update DWORD3 in the buffer */
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Store(CTRL, CDW3)
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} Else {
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Or(CDW1, 4, CDW1) /* Unrecognized UUID */
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}
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Return (Arg3)
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}
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}
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}
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#include "acpi/pci-crs.asl"
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#include "acpi/hpet.asl"
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/* VGA */
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Scope(\_SB.PCI0) {
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Device(VGA) {
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Name(_ADR, 0x00010000)
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Method(_S1D, 0, NotSerialized) {
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Return (0x00)
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}
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Method(_S2D, 0, NotSerialized) {
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Return (0x00)
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}
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Method(_S3D, 0, NotSerialized) {
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Return (0x00)
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}
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}
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}
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/* LPC ISA bridge */
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Scope(\_SB.PCI0) {
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/* PCI D31:f0 LPC ISA bridge */
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Device(ISA) {
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/* PCI D31:f0 */
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Name(_ADR, 0x001f0000)
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/* ICH9 PCI to ISA irq remapping */
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OperationRegion(PIRQ, PCI_Config, 0x60, 0x0c)
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OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
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Field(LPCD, AnyAcc, NoLock, Preserve) {
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COMA, 3,
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, 1,
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COMB, 3,
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Offset(0x01),
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LPTD, 2,
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, 2,
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FDCD, 2
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}
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OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
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Field(LPCE, AnyAcc, NoLock, Preserve) {
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CAEN, 1,
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CBEN, 1,
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LPEN, 1,
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FDEN, 1
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}
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}
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}
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#include "acpi/isa.asl"
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/* PCI IRQs */
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/* Zero => PIC mode, One => APIC Mode */
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Name(\PICF, Zero)
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Method(\_PIC, 1, NotSerialized) {
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Store(Arg0, \PICF)
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}
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|
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Scope(\_SB) {
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Scope(PCI0) {
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#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
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Package() { nr##ffff, 0, lnk0, 0 }, \
|
||||
Package() { nr##ffff, 1, lnk1, 0 }, \
|
||||
Package() { nr##ffff, 2, lnk2, 0 }, \
|
||||
Package() { nr##ffff, 3, lnk3, 0 }
|
||||
|
||||
#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
|
||||
#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
|
||||
#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
|
||||
#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
|
||||
|
||||
#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
|
||||
#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
|
||||
#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
|
||||
#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
|
||||
|
||||
Name(PRTP, Package() {
|
||||
prt_slot_lnkE(0x0000),
|
||||
prt_slot_lnkF(0x0001),
|
||||
prt_slot_lnkG(0x0002),
|
||||
prt_slot_lnkH(0x0003),
|
||||
prt_slot_lnkE(0x0004),
|
||||
prt_slot_lnkF(0x0005),
|
||||
prt_slot_lnkG(0x0006),
|
||||
prt_slot_lnkH(0x0007),
|
||||
prt_slot_lnkE(0x0008),
|
||||
prt_slot_lnkF(0x0009),
|
||||
prt_slot_lnkG(0x000a),
|
||||
prt_slot_lnkH(0x000b),
|
||||
prt_slot_lnkE(0x000c),
|
||||
prt_slot_lnkF(0x000d),
|
||||
prt_slot_lnkG(0x000e),
|
||||
prt_slot_lnkH(0x000f),
|
||||
prt_slot_lnkE(0x0010),
|
||||
prt_slot_lnkF(0x0011),
|
||||
prt_slot_lnkG(0x0012),
|
||||
prt_slot_lnkH(0x0013),
|
||||
prt_slot_lnkE(0x0014),
|
||||
prt_slot_lnkF(0x0015),
|
||||
prt_slot_lnkG(0x0016),
|
||||
prt_slot_lnkH(0x0017),
|
||||
prt_slot_lnkE(0x0018),
|
||||
|
||||
/* INTA -> PIRQA for slot 25 - 31
|
||||
see the default value of D<N>IR */
|
||||
prt_slot_lnkA(0x0019),
|
||||
prt_slot_lnkA(0x001a),
|
||||
prt_slot_lnkA(0x001b),
|
||||
prt_slot_lnkA(0x001c),
|
||||
prt_slot_lnkA(0x001d),
|
||||
|
||||
/* PCIe->PCI bridge. use PIRQ[E-H] */
|
||||
prt_slot_lnkE(0x001e),
|
||||
|
||||
prt_slot_lnkA(0x001f)
|
||||
})
|
||||
|
||||
#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
|
||||
Package() { nr##ffff, 0, gsi0, 0 }, \
|
||||
Package() { nr##ffff, 1, gsi1, 0 }, \
|
||||
Package() { nr##ffff, 2, gsi2, 0 }, \
|
||||
Package() { nr##ffff, 3, gsi3, 0 }
|
||||
|
||||
#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
|
||||
#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
|
||||
#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
|
||||
#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
|
||||
|
||||
#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
|
||||
#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
|
||||
#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
|
||||
#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
|
||||
|
||||
Name(PRTA, Package() {
|
||||
prt_slot_gsiE(0x0000),
|
||||
prt_slot_gsiF(0x0001),
|
||||
prt_slot_gsiG(0x0002),
|
||||
prt_slot_gsiH(0x0003),
|
||||
prt_slot_gsiE(0x0004),
|
||||
prt_slot_gsiF(0x0005),
|
||||
prt_slot_gsiG(0x0006),
|
||||
prt_slot_gsiH(0x0007),
|
||||
prt_slot_gsiE(0x0008),
|
||||
prt_slot_gsiF(0x0009),
|
||||
prt_slot_gsiG(0x000a),
|
||||
prt_slot_gsiH(0x000b),
|
||||
prt_slot_gsiE(0x000c),
|
||||
prt_slot_gsiF(0x000d),
|
||||
prt_slot_gsiG(0x000e),
|
||||
prt_slot_gsiH(0x000f),
|
||||
prt_slot_gsiE(0x0010),
|
||||
prt_slot_gsiF(0x0011),
|
||||
prt_slot_gsiG(0x0012),
|
||||
prt_slot_gsiH(0x0013),
|
||||
prt_slot_gsiE(0x0014),
|
||||
prt_slot_gsiF(0x0015),
|
||||
prt_slot_gsiG(0x0016),
|
||||
prt_slot_gsiH(0x0017),
|
||||
prt_slot_gsiE(0x0018),
|
||||
|
||||
/*
|
||||
* INTA -> PIRQA for slot 25 - 31, but 30
|
||||
* see the default value of D<N>IR
|
||||
*/
|
||||
prt_slot_gsiA(0x0019),
|
||||
prt_slot_gsiA(0x001a),
|
||||
prt_slot_gsiA(0x001b),
|
||||
prt_slot_gsiA(0x001c),
|
||||
prt_slot_gsiA(0x001d),
|
||||
|
||||
/* PCIe->PCI bridge. use PIRQ[E-H] */
|
||||
prt_slot_gsiE(0x001e),
|
||||
|
||||
prt_slot_gsiA(0x001f)
|
||||
})
|
||||
|
||||
Method(_PRT, 0, NotSerialized) {
|
||||
/*
|
||||
* PCI IRQ routing table,
|
||||
* example from ACPI 2.0a
|
||||
* specification, section 6.2.8.1
|
||||
* Note: we provide the same info
|
||||
* as the PCI routing table
|
||||
* of the Bochs BIOS
|
||||
*/
|
||||
If (LEqual(\PICF, Zero)) {
|
||||
Return (PRTP)
|
||||
} Else {
|
||||
Return (PRTA)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
|
||||
PRQA, 8,
|
||||
PRQB, 8,
|
||||
PRQC, 8,
|
||||
PRQD, 8,
|
||||
|
||||
Offset(0x08),
|
||||
PRQE, 8,
|
||||
PRQF, 8,
|
||||
PRQG, 8,
|
||||
PRQH, 8
|
||||
}
|
||||
|
||||
Method(IQST, 1, NotSerialized) {
|
||||
/* _STA method - get status */
|
||||
If (And(0x80, Arg0)) {
|
||||
Return (0x09)
|
||||
}
|
||||
Return (0x0b)
|
||||
}
|
||||
Method(IQCR, 1, NotSerialized) {
|
||||
/* _CRS method - get current settings */
|
||||
Name(PRR0, ResourceTemplate() {
|
||||
Interrupt(, Level, ActiveHigh, Shared) { 0 }
|
||||
})
|
||||
CreateDWordField(PRR0, 0x05, PRRI)
|
||||
Store(And(Arg0, 0x0f), PRRI)
|
||||
Return (PRR0)
|
||||
}
|
||||
|
||||
#define define_link(link, uid, reg) \
|
||||
Device(link) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
Name(_PRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
5, 10, 11 \
|
||||
} \
|
||||
}) \
|
||||
Method(_STA, 0, NotSerialized) { \
|
||||
Return (IQST(reg)) \
|
||||
} \
|
||||
Method(_DIS, 0, NotSerialized) { \
|
||||
Or(reg, 0x80, reg) \
|
||||
} \
|
||||
Method(_CRS, 0, NotSerialized) { \
|
||||
Return (IQCR(reg)) \
|
||||
} \
|
||||
Method(_SRS, 1, NotSerialized) { \
|
||||
CreateDWordField(Arg0, 0x05, PRRI) \
|
||||
Store(PRRI, reg) \
|
||||
} \
|
||||
}
|
||||
|
||||
define_link(LNKA, 0, PRQA)
|
||||
define_link(LNKB, 1, PRQB)
|
||||
define_link(LNKC, 2, PRQC)
|
||||
define_link(LNKD, 3, PRQD)
|
||||
define_link(LNKE, 4, PRQE)
|
||||
define_link(LNKF, 5, PRQF)
|
||||
define_link(LNKG, 6, PRQG)
|
||||
define_link(LNKH, 7, PRQH)
|
||||
|
||||
#define define_gsi_link(link, uid, gsi) \
|
||||
Device(link) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
Name(_PRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
gsi \
|
||||
} \
|
||||
}) \
|
||||
Name(_CRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
gsi \
|
||||
} \
|
||||
}) \
|
||||
Method(_SRS, 1, NotSerialized) { \
|
||||
} \
|
||||
}
|
||||
|
||||
define_gsi_link(GSIA, 0, 0x10)
|
||||
define_gsi_link(GSIB, 0, 0x11)
|
||||
define_gsi_link(GSIC, 0, 0x12)
|
||||
define_gsi_link(GSID, 0, 0x13)
|
||||
define_gsi_link(GSIE, 0, 0x14)
|
||||
define_gsi_link(GSIF, 0, 0x15)
|
||||
define_gsi_link(GSIG, 0, 0x16)
|
||||
define_gsi_link(GSIH, 0, 0x17)
|
||||
}
|
||||
|
||||
/* General purpose events */
|
||||
|
||||
Scope(\_GPE) {
|
||||
Name(_HID, "ACPI0006")
|
||||
|
||||
Method(_L00) {
|
||||
}
|
||||
Method(_L01) {
|
||||
}
|
||||
Method(_L02) {
|
||||
}
|
||||
Method(_L03) {
|
||||
}
|
||||
Method(_L04) {
|
||||
}
|
||||
Method(_L05) {
|
||||
}
|
||||
Method(_L06) {
|
||||
}
|
||||
Method(_L07) {
|
||||
}
|
||||
Method(_L08) {
|
||||
}
|
||||
Method(_L09) {
|
||||
}
|
||||
Method(_L0A) {
|
||||
}
|
||||
Method(_L0B) {
|
||||
}
|
||||
Method(_L0C) {
|
||||
}
|
||||
Method(_L0D) {
|
||||
}
|
||||
Method(_L0E) {
|
||||
}
|
||||
Method(_L0F) {
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user