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https://xff.cz/git/u-boot/
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board/adp-ag102: add configuration of adp-ag102
board: Add config file of board adp-ag102 Add adp-ag102 into boards.cfg Add adp-ag102 into MAINTAINERS doc: add README of ag102 Signed-off-by: Macpaul Lin <macpaul@andestech.com>
This commit is contained in:
Macpaul Lin
Macpaul Lin
@@ -1191,6 +1191,7 @@ Macpaul Lin <macpaul@andestech.com>
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ADP-AG101 N1213 (AG101 SoC)
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ADP-AG101 N1213 (AG101 SoC)
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ADP-AG101P N1213 (AG101P XC5 FPGA)
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ADP-AG101P N1213 (AG101P XC5 FPGA)
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ADP-AG102 N1213f (AG102 SoC with FPU)
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#########################################################################
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#########################################################################
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# OpenRISC Systems: #
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# OpenRISC Systems: #
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@@ -370,6 +370,7 @@ incaip_150MHz mips mips32 incaip -
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qi_lb60 mips xburst qi_lb60 qi
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qi_lb60 mips xburst qi_lb60 qi
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adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101
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adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101
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adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101
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adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101
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adp-ag102 nds32 n1213 adp-ag102 AndesTech ag102
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nios2-generic nios2 nios2 nios2-generic altera
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nios2-generic nios2 nios2 nios2-generic altera
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PCI5441 nios2 nios2 pci5441 psyent
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PCI5441 nios2 nios2 pci5441 psyent
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PK1C20 nios2 nios2 pk1c20 psyent
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PK1C20 nios2 nios2 pk1c20 psyent
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36
doc/README.ag102
Normal file
36
doc/README.ag102
Normal file
@@ -0,0 +1,36 @@
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Andes Technology SoC AG102
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==========================
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AG102 is the second SoC produced by Andes Technology using N1213 CPU core
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with FPU and DDR contoller support.
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AG102 has integrated both AHB and APB bus and many periphals for application
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and product development.
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ADP-AG102
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=========
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ADP-AG102 is the SoC with AG102 hardcore CPU.
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Configurations
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==============
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CONFIG_MEM_REMAP:
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Doing memory remap is essential for preparing some non-OS or RTOS
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applications.
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CONFIG_SKIP_LOWLEVEL_INIT:
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If you want to boot this system from SPI ROM and bypass e-bios (the
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other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
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in "include/configs/adp-ag102.h".
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Build and boot steps
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====================
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build:
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1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
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2. Use `make adp-ag102` in u-boot root to build the image.
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Burn u-boot to SPI ROM:
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====================
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This section will be added later.
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375
include/configs/adp-ag102.h
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375
include/configs/adp-ag102.h
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@@ -0,0 +1,375 @@
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/ag102.h>
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/*
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* CPU and Board Configuration Options
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*/
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#define CONFIG_ADP_AG102
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#define CONFIG_USE_INTERRUPT
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_MEM_REMAP
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#endif
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_TEXT_BASE 0x04200000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#endif
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/*
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* Timer
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*/
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/*
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* According to the discussion in u-boot mailing list before,
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* CONFIG_SYS_HZ at 1000 is mandatory.
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*/
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_CLK_FREQ (66000000 * 2)
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#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
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/*
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* Use Externel CLOCK or PCLK
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*/
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#undef CONFIG_FTRTC010_EXTCLK
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#ifndef CONFIG_FTRTC010_EXTCLK
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#define CONFIG_FTRTC010_PCLK
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#endif
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#ifdef CONFIG_FTRTC010_EXTCLK
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#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
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#else
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#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
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#endif
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#define TIMER_LOAD_VAL 0xffffffff
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/*
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* Real Time Clock
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*/
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#define CONFIG_RTC_FTRTC010
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/*
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* Real Time Clock Divider
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* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
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*/
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#define OSC_5MHZ (5*1000000)
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#define OSC_CLK (2*OSC_5MHZ)
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#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
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/*
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* Serial console configuration
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*/
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/* FTUART is a high speed NS 16C550A compatible UART */
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Ethernet
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */
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#define CONFIG_SYS_DISCOVER_PHY
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#define CONFIG_FTGMAC100
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#define CONFIG_FTGMAC100_EGIGA
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#define CONFIG_BOOTDELAY 3
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/*
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* SD (MMC) controller
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*/
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#define CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_FTSDC010
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#define CONFIG_FTSDC010_NUMBER 1
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#define CONFIG_FTSDC010_SDIO
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_ELF
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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/*
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* PCI
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*/
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#define CONFIG_PCI
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#define CONFIG_FTPCI100
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#define CONFIG_FTPCI100_MEM_BASE 0xa0000000
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#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */
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#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */
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#define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50
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#define CONFIG_PCI_MEM_BUS 0xa0000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */
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#define CONFIG_PCI_IO_BUS 0x90000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */
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/*
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* USB
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*/
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#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
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#if defined(CONFIG_FTPCI100)
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#define __io /* enable outl & inl */
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#define CONFIG_CMD_USB
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_EHCI
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#define CONFIG_PCI_EHCI_DEVICE 0
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#define CONFIG_USB_EHCI_PCI
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#define CONFIG_PREBOOT "usb start;"
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#endif /* #if defiend(CONFIG_FTPCI100) */
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#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
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/*
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* IDE/ATA stuff
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*/
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#define __io
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#define CONFIG_IDE_AHB
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#define CONFIG_IDE_FTIDE020
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CONFIG_IDE_PREINIT 1 /* preinit for ide */
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/* max: 2 IDE busses */
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#define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */
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/* max: 2 drives per IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SUPPORT_VFAT
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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||||||
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||||||
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/* max number of command args */
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||||||
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#define CONFIG_SYS_MAXARGS 16
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||||||
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||||||
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/* Boot Argument Buffer Size */
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||||||
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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||||||
|
|
||||||
|
/*
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||||||
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* Stack sizes
|
||||||
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*
|
||||||
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* The stack sizes are set up in start.S using the settings below
|
||||||
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*/
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||||||
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
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||||||
|
|
||||||
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/*
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||||||
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* Size of malloc() pool
|
||||||
|
*/
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||||||
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
|
||||||
|
|
||||||
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/*
|
||||||
|
* size in bytes reserved for initial data
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AHB Controller configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_FTAHBC020S
|
||||||
|
|
||||||
|
#ifdef CONFIG_FTAHBC020S
|
||||||
|
#include <faraday/ftahbc020s.h>
|
||||||
|
|
||||||
|
/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
|
||||||
|
#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
|
||||||
|
|
||||||
|
/*
|
||||||
|
* CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
|
||||||
|
* hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
|
||||||
|
* in C language.
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
|
||||||
|
(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
|
||||||
|
FTAHBC020S_SLAVE_BSR_SIZE(0xb))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Watchdog
|
||||||
|
*/
|
||||||
|
#define CONFIG_FTWDT010_WATCHDOG
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PCU Power Control Unit configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_ANDES_PCU
|
||||||
|
|
||||||
|
#ifdef CONFIG_ANDES_PCU
|
||||||
|
#include <andestech/andes_pcu.h>
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DDR DRAM controller configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_DWCDDR21MCTL
|
||||||
|
|
||||||
|
#ifdef CONFIG_DWCDDR21MCTL
|
||||||
|
#include <synopsys/dwcddr21mctl.h>
|
||||||
|
/* DCR:
|
||||||
|
* 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
|
||||||
|
* 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
|
||||||
|
* 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
|
||||||
|
* 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
|
||||||
|
* 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \
|
||||||
|
DWCDDR21MCTL_CCR_DFTLM(0x4) | \
|
||||||
|
DWCDDR21MCTL_CCR_HOSTEN(0x1))
|
||||||
|
|
||||||
|
/* 0x04: 0x000020d4 */
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca
|
||||||
|
|
||||||
|
/* 0x08: 0x0000000f */
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f
|
||||||
|
|
||||||
|
/* 0x10: 0x00034812 */
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \
|
||||||
|
DWCDDR21MCTL_DRR_TRFPRD(0x0348))
|
||||||
|
/* 0x24 */
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0)
|
||||||
|
|
||||||
|
/* 0x4c: 0x00000040 */
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040
|
||||||
|
|
||||||
|
/* 0x5c: 0x000055CF */
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf
|
||||||
|
|
||||||
|
/* 0xa4: 0x00100000 */
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \
|
||||||
|
DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
|
||||||
|
DWCDDR21MCTL_DTAR_DTCOL(0x0))
|
||||||
|
/* 0x1f0: 0x00000852 */
|
||||||
|
#define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \
|
||||||
|
DWCDDR21MCTL_MR_CL(0x5) | \
|
||||||
|
DWCDDR21MCTL_MR_BL(0x2))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Physical Memory Map
|
||||||
|
*/
|
||||||
|
#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
|
||||||
|
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
|
||||||
|
#if defined(CONFIG_MEM_REMAP)
|
||||||
|
#define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/
|
||||||
|
#endif
|
||||||
|
#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
|
||||||
|
#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||||
|
#define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
|
||||||
|
|
||||||
|
#ifdef CONFIG_MEM_REMAP
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
|
||||||
|
GENERATED_GBL_DATA_SIZE)
|
||||||
|
#else
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
|
||||||
|
GENERATED_GBL_DATA_SIZE)
|
||||||
|
#endif /* CONFIG_MEM_REMAP */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Load address and memory test area should agree with
|
||||||
|
* board/faraday/a320/config.mk
|
||||||
|
* Be careful not to overwrite U-boot itself.
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x0CF00000
|
||||||
|
|
||||||
|
/* memtest works on 63 MB in DRAM */
|
||||||
|
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
|
||||||
|
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Static memory controller configuration
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FLASH and environment organization
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_NO_FLASH
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Env Storage Settings
|
||||||
|
*/
|
||||||
|
#define CONFIG_ENV_IS_NOWHERE
|
||||||
|
#define CONFIG_ENV_SIZE 4096
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */
|
||||||
Reference in New Issue
Block a user