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clk: meson: reset mmc clock on probe

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On some SoCs, depending on the boot device, the MMC clock block may be
left in a weird state by the ROM code, in which no decent clock may be
provided. Reset the related register to make sure a sane MMC clock is
ready for the controller.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Jerome Brunet
2020-03-05 12:12:37 +01:00
committed by Neil Armstrong
parent 0392416fb1
commit b3d69aa596
3 changed files with 21 additions and 0 deletions
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7
drivers/clk/meson/axg.c
View File

@@ -291,6 +291,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
/*
* Depending on the boot src, the state of the MMC clock might
* be different. Reset it to make sure we won't get stuck
*/
regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
debug("meson-clk-axg: probed\n");
return 0;

7
drivers/clk/meson/g12a.c
View File

@@ -978,6 +978,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
/*
* Depending on the boot src, the state of the MMC clock might
* be different. Reset it to make sure we won't get stuck
*/
regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
debug("meson-clk-g12a: probed\n");
return 0;

7
drivers/clk/meson/gxbb.c
View File

@@ -887,6 +887,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
/*
* Depending on the boot src, the state of the MMC clock might
* be different. Reset it to make sure we won't get stuck
*/
regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
debug("meson-clk: probed\n");
return 0;