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riscv: fix use of incorrectly sized variables

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The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
several places. Fix this.
In addition, BITS_PER_LONG is set to 64 on RV64I systems.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Lukas Auer
2018-11-22 11:26:17 +01:00
committed by Andes
parent 776e6335bf
commit b2c860c6dc
4 changed files with 15 additions and 11 deletions
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10
arch/riscv/lib/interrupts.c
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@@ -12,7 +12,7 @@
#include <asm/system.h>
#include <asm/encoding.h>
static void _exit_trap(int code, uint epc, struct pt_regs *regs);
static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs);
int interrupt_init(void)
{
@@ -34,9 +34,9 @@ int disable_interrupts(void)
return 0;
}
uint handle_trap(uint mcause, uint epc, struct pt_regs *regs)
ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs)
{
uint is_int;
ulong is_int;
is_int = (mcause & MCAUSE_INT);
if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
@@ -60,7 +60,7 @@ __attribute__((weak)) void timer_interrupt(struct pt_regs *regs)
{
}
static void _exit_trap(int code, uint epc, struct pt_regs *regs)
static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
{
static const char * const exception_code[] = {
"Instruction address misaligned",
@@ -70,6 +70,6 @@ static void _exit_trap(int code, uint epc, struct pt_regs *regs)
"Load address misaligned"
};
printf("exception code: %d , %s , epc %08x , ra %08lx\n",
printf("exception code: %ld , %s , epc %lx , ra %lx\n",
code, exception_code[code], epc, regs->ra);
}