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	Minor code cleanup.
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		| @@ -41,8 +41,6 @@ struct sys_ctrl { | |||||||
|     /* TODO: finish these */ |     /* TODO: finish these */ | ||||||
| }; | }; | ||||||
|  |  | ||||||
|  |  | ||||||
|  |  | ||||||
| /* Fast ethernet controller registers | /* Fast ethernet controller registers | ||||||
|  */ |  */ | ||||||
| typedef struct fec { | typedef struct fec { | ||||||
| @@ -69,18 +67,18 @@ typedef struct fec { | |||||||
| 	uint	fec_addr_high;	/* upper 16 bits of station address  */ /* PAUR */ | 	uint	fec_addr_high;	/* upper 16 bits of station address  */ /* PAUR */ | ||||||
| 	uint	fec_opd;	/* opcode + pause duration	10EC*/	/* OPD */ | 	uint	fec_opd;	/* opcode + pause duration	10EC*/	/* OPD */ | ||||||
| 	uint	res9[10];	/* reserved			10F0*/ | 	uint	res9[10];	/* reserved			10F0*/ | ||||||
| 	uint    fec_ihash_table_high;	/* upper 32-bits of individual hash *//* IAUR */ | 	uint	fec_ihash_table_high;	/* upper 32-bits of individual hash */ /* IAUR */ | ||||||
| 	uint    fec_ihash_table_low;	/* lower 32-bits of individual hash  *//* IALR */ | 	uint	fec_ihash_table_low;	/* lower 32-bits of individual hash */ /* IALR */ | ||||||
| 	uint    fec_ghash_table_high;	/* upper 32-bits of group hash  *//* GAUR */ | 	uint	fec_ghash_table_high;	/* upper 32-bits of group hash	*/ /* GAUR */ | ||||||
| 	uint    fec_ghash_table_low;	/* lower 32-bits of group hash  *//* GALR */ | 	uint	fec_ghash_table_low;	/* lower 32-bits of group hash	*/ /* GALR */ | ||||||
| 	uint	res10[7];	/* reserved			1128*/ | 	uint	res10[7];	/* reserved			1128*/ | ||||||
| 	uint	fec_tfwr;	/* Transmit FIFO watermark	1144*/	/* TFWR */ | 	uint	fec_tfwr;	/* Transmit FIFO watermark	1144*/	/* TFWR */ | ||||||
| 	uint	res11;		/* reserved			1148*/ | 	uint	res11;		/* reserved			1148*/ | ||||||
| 	uint    fec_r_bound;	/* FIFO Receive Bound Register = end of *//* FRBR */ | 	uint	fec_r_bound;	/* FIFO Receive Bound Register = end of */ /* FRBR */ | ||||||
| 	uint    fec_r_fstart;	/* FIFO Receive FIfo Start Registers =  *//* FRSR */ | 	uint	fec_r_fstart;	/* FIFO Receive FIfo Start Registers =	*/ /* FRSR */ | ||||||
| 	uint	res12[11];	/* reserved			1154*/ | 	uint	res12[11];	/* reserved			1154*/ | ||||||
| 	uint    fec_r_des_start;/* beginning of Rx descriptor ring    1180*//* ERDSR */ | 	uint	fec_r_des_start;/* beginning of Rx descriptor ring    1180*/ /* ERDSR */ | ||||||
| 	uint    fec_x_des_start;/* beginning of Tx descriptor ring    1184*//* ETDSR */ | 	uint	fec_x_des_start;/* beginning of Tx descriptor ring    1184*/ /* ETDSR */ | ||||||
| 	uint	fec_r_buff_size;/* Rx buffer size		1188*/	/* EMRBR */ | 	uint	fec_r_buff_size;/* Rx buffer size		1188*/	/* EMRBR */ | ||||||
| } fec_t; | } fec_t; | ||||||
|  |  | ||||||
|   | |||||||
| @@ -68,7 +68,7 @@ | |||||||
| #define CFG_ENV_IS_IN_FLASH	1 | #define CFG_ENV_IS_IN_FLASH	1 | ||||||
| #endif | #endif | ||||||
|  |  | ||||||
| //#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) | /*#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */ | ||||||
| #define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB)) | #define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB)) | ||||||
|  |  | ||||||
| /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | ||||||
|   | |||||||
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