dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-10-21 01:51:11 +02:00
Code Issues Packages Projects Releases Wiki Activity

powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs

Browse Source 
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Prabhakar Kushwaha
2011-02-01 15:55:58 +00:00
committed by Kumar Gala
parent 2d7534a344
commit b03a466d6c
4 changed files with 60 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/pci/fsl_pci_init.c
View File

@@ -317,6 +317,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
temp32 = 0;
pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32);
temp32 &= ~0x03; /* Disable ASPM */
pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32);
udelay(1);
#endif
if (pcie_cap == PCI_CAP_ID_EXP) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
enabled = ltssm >= PCI_LTSSM_L0;