From c6df0e2ffdc468ce34a7bc77fa5a298e0359e7a0 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 3 Dec 2020 11:18:30 +0200 Subject: [PATCH 01/18] net: phy: micrel: add support for DLL setup on ksz9131 Add support for DLL setup on KSZ9131. Signed-off-by: Claudiu Beznea --- drivers/net/phy/micrel_ksz90x1.c | 63 +++++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index f0032e8ce1..d6694c5cd8 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -396,9 +396,70 @@ static struct phy_driver ksz9031_driver = { /* * KSZ9131 */ + +#define KSZ9131RN_MMD_COMMON_CTRL_REG 2 +#define KSZ9131RN_RXC_DLL_CTRL 76 +#define KSZ9131RN_TXC_DLL_CTRL 77 +#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12) +#define KSZ9131RN_DLL_ENABLE_DELAY 0 +#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12) + +static int ksz9131_config_rgmii_delay(struct phy_device *phydev) +{ + struct phy_driver *drv = phydev->drv; + u16 rxcdll_val, txcdll_val, val; + int ret; + + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; + txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_ID: + rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; + txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_RXID: + rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; + txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; + break; + case PHY_INTERFACE_MODE_RGMII_TXID: + rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY; + txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY; + break; + default: + return 0; + } + + val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG, + KSZ9131RN_RXC_DLL_CTRL); + val &= ~KSZ9131RN_DLL_CTRL_BYPASS; + val |= rxcdll_val; + ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG, + KSZ9131RN_RXC_DLL_CTRL, val); + if (ret) + return ret; + + val = drv->readext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG, + KSZ9131RN_TXC_DLL_CTRL); + + val &= ~KSZ9131RN_DLL_CTRL_BYPASS; + val |= txcdll_val; + ret = drv->writeext(phydev, 0, KSZ9131RN_MMD_COMMON_CTRL_REG, + KSZ9131RN_TXC_DLL_CTRL, val); + + return ret; +} + static int ksz9131_config(struct phy_device *phydev) { - /* TBD: Implement Skew values for dts */ + int ret; + + if (phy_interface_is_rgmii(phydev)) { + ret = ksz9131_config_rgmii_delay(phydev); + if (ret) + return ret; + } /* add an option to disable the gigabit feature of this PHY */ if (env_get("disable_giga")) { From 36dfddc5536c4757e72116d66eaabb71f21fbd8e Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 3 Dec 2020 11:18:31 +0200 Subject: [PATCH 02/18] net: phy: micrel: fix typo Fix typo. Signed-off-by: Claudiu Beznea --- drivers/net/phy/micrel_ksz90x1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index d6694c5cd8..77fad4a8fc 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -491,7 +491,7 @@ static int ksz9131_config(struct phy_device *phydev) } static struct phy_driver ksz9131_driver = { - .name = "Micrel ksz9031", + .name = "Micrel ksz9131", .uid = PHY_ID_KSZ9131, .mask = MII_KSZ9x31_SILICON_REV_MASK, .features = PHY_GBIT_FEATURES, From 7cdcf0cb69f2b3e64194a1ab8845887737c2f795 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 5 Jan 2021 10:49:10 +0200 Subject: [PATCH 03/18] dt-bindings: pinctrl: at91-pio4: update license to SPDX style Update license header to SPDX style Signed-off-by: Eugen Hristev --- include/dt-bindings/pinctrl/at91.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h index 616f5ce400..5afb1863c3 100644 --- a/include/dt-bindings/pinctrl/at91.h +++ b/include/dt-bindings/pinctrl/at91.h @@ -1,9 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides constants for most at91 pinctrl bindings. * * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD - * - * GPLv2 only */ #ifndef __DT_BINDINGS_AT91_PINCTRL_H__ From 63c27c3e66697db779ae4cd931f8ccfd84838ae5 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 5 Jan 2021 10:50:06 +0200 Subject: [PATCH 04/18] dt-bindings: pinctrl: at91-pio4: add property for drive strength Add drive strength property which is equivalent with the one in Linux Signed-off-by: Eugen Hristev --- doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt index a376c6fba5..9252dc154e 100644 --- a/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -28,6 +28,8 @@ Optional properties: - GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable, input-debounce. +- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for +high drive. The default value is low drive. Example: From 864a4144ba30f405b8a8e136cffb8b3ef424058d Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 5 Jan 2021 10:51:53 +0200 Subject: [PATCH 05/18] pinctrl: at91-pio4: convert to dev_read_prop Use dev_read_prop instead of using the fdt_read_property which reads from the GD struct's fdt. This way the node is accessed via the device config instead of the global struct, which makes code more portable and GD independent. Signed-off-by: Eugen Hristev --- drivers/pinctrl/pinctrl-at91-pio4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 1aba8a9150..eff43380df 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -36,7 +36,7 @@ static const struct pinconf_param conf_params[] = { { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, }; -static u32 atmel_pinctrl_get_pinconf(const void *blob, int node) +static u32 atmel_pinctrl_get_pinconf(struct udevice *config) { const struct pinconf_param *params; u32 param, arg, conf = 0; @@ -44,7 +44,7 @@ static u32 atmel_pinctrl_get_pinconf(const void *blob, int node) for (i = 0; i < ARRAY_SIZE(conf_params); i++) { params = &conf_params[i]; - if (!fdt_get_property(blob, node, params->property, NULL)) + if (!dev_read_prop(config, params->property, NULL)) continue; param = params->param; @@ -115,7 +115,7 @@ static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config) u32 i, conf; int count; - conf = atmel_pinctrl_get_pinconf(blob, node); + conf = atmel_pinctrl_get_pinconf(config); count = fdtdec_get_int_array_count(blob, node, "pinmux", cells, ARRAY_SIZE(cells)); From 417eca09bf2b325bf0c6399c6b58a0692711542d Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Tue, 5 Jan 2021 10:54:01 +0200 Subject: [PATCH 06/18] pinctrl: at91-pio4: implement drive strength support Implement drive strength support, by preserving the same bindings as in Linux. Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/include/mach/atmel_pio4.h | 1 + drivers/pinctrl/pinctrl-at91-pio4.c | 8 ++++++++ include/dt-bindings/pinctrl/at91.h | 4 ++++ 3 files changed, 13 insertions(+) diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h index f348b05bc8..35ac7b2d40 100644 --- a/arch/arm/mach-at91/include/mach/atmel_pio4.h +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h @@ -52,6 +52,7 @@ struct atmel_pio4_port { #define ATMEL_PIO_DRVSTR_LO (1 << 16) #define ATMEL_PIO_DRVSTR_ME (2 << 16) #define ATMEL_PIO_DRVSTR_HI (3 << 16) +#define ATMEL_PIO_DRVSTR_OFFSET 16 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index eff43380df..3a5143adc3 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -34,6 +34,7 @@ static const struct pinconf_param conf_params[] = { { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "atmel,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, }; static u32 atmel_pinctrl_get_pinconf(struct udevice *config) @@ -41,6 +42,7 @@ static u32 atmel_pinctrl_get_pinconf(struct udevice *config) const struct pinconf_param *params; u32 param, arg, conf = 0; u32 i; + u32 val; for (i = 0; i < ARRAY_SIZE(conf_params); i++) { params = &conf_params[i]; @@ -82,6 +84,12 @@ static u32 atmel_pinctrl_get_pinconf(struct udevice *config) conf |= ATMEL_PIO_IFSCEN_MASK; } break; + case PIN_CONFIG_DRIVE_STRENGTH: + dev_read_u32(config, params->property, &val); + conf &= (~ATMEL_PIO_DRVSTR_MASK); + conf |= (val << ATMEL_PIO_DRVSTR_OFFSET) + & ATMEL_PIO_DRVSTR_MASK; + break; default: printf("%s: Unsupported configuration parameter: %u\n", __func__, param); diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h index 5afb1863c3..3831f91fb3 100644 --- a/include/dt-bindings/pinctrl/at91.h +++ b/include/dt-bindings/pinctrl/at91.h @@ -42,4 +42,8 @@ #define AT91_PERIPH_C 3 #define AT91_PERIPH_D 4 +#define ATMEL_PIO_DRVSTR_LO 1 +#define ATMEL_PIO_DRVSTR_ME 2 +#define ATMEL_PIO_DRVSTR_HI 3 + #endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ From 6f889819f3f3992f4e61c7b860f2958c9f1afab0 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 8 Jan 2021 14:40:17 +0200 Subject: [PATCH 07/18] configs: at91: Fix the involuntarily disablement of NAND PMECC SPL_GENERATE_ATMEL_PMECC_HEADER selects: ATMEL_NAND_HWECC [=y] && ATMEL_NAND_HW_PMECC [=y]. With the removal of SPL_GENERATE_ATMEL_PMECC_HEADER, ATMEL_NAND_HW_PMECC and ATMEL_NAND_HWECC were no longer selected. Also, when the SPL_GENERATE_ATMEL_PMECC_HEADER was removed, the configs were not updated using savedefconfig, thus the 'commit d168bcb6fe39 ("configs: Resync with savedefconfig")' further removes the CONFIG_PMECC_CAP value. Update defconfigs and add CONFIG_ATMEL_NAND_HW_PMECC, which selects ATMEL_NAND_HWECC, in order to restore NAND PMECC support. Restore CONFIG_PMECC_CAP value. Fixes: 57f76c2a47 ("configs: at91: remove SPL_GENERATE_ATMEL_PMECC_HEADER from non-nand configs") Signed-off-by: Tudor Ambarus --- configs/at91sam9n12ek_mmc_defconfig | 1 + configs/at91sam9n12ek_spiflash_defconfig | 1 + configs/at91sam9x5ek_mmc_defconfig | 1 + configs/at91sam9x5ek_spiflash_defconfig | 1 + configs/sama5d36ek_cmp_mmc_defconfig | 1 + configs/sama5d36ek_cmp_spiflash_defconfig | 1 + configs/sama5d3_xplained_mmc_defconfig | 1 + configs/sama5d3xek_mmc_defconfig | 2 ++ configs/sama5d3xek_spiflash_defconfig | 2 ++ configs/sama5d4_xplained_spiflash_defconfig | 2 ++ configs/sama5d4ek_mmc_defconfig | 1 + configs/sama5d4ek_spiflash_defconfig | 2 ++ 12 files changed, 16 insertions(+) diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 74a28a3029..ad6ab85153 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -42,6 +42,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 6a340f5a01..c6ac36652b 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -44,6 +44,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index d48d2d7333..9acdbb8445 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -45,6 +45,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index eb935d6ddc..25de37f496 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -47,6 +47,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index 22c1134658..eb7eb80969 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -46,6 +46,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 8fc183faa2..556ea2f29e 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -48,6 +48,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index c839b4fe6e..0aadf2a5c3 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -65,6 +65,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 70c6e30718..5c0c5cb6b5 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -70,6 +70,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=4 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 5a06518c9c..109ac9f522 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -71,6 +71,8 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=4 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index d9ad9cc522..a29bbaed63 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -67,6 +67,8 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=8 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index d91a6f6644..9c9862c1d5 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -61,6 +61,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 5ebd1cc9b1..e62619f2ce 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -64,6 +64,8 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=8 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y From 58b1d680d139113b7ce91aa2d22bc71d74a9715e Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 8 Jan 2021 14:40:18 +0200 Subject: [PATCH 08/18] configs: at91: Fix wrong definitions for CONFIG_PMECC_CAP When CONFIG_ATMEL_NAND_HW_PMECC is set, CONFIG_PMECC_CAP defaults to the value of 2. At the conversion to Kconfig for the PMECC config values, some boards/defconfigs were wrongly configured. Update CONFIG_PMECC_CAP to the PMECC_CAP value before the conversion. Fixes: 49ad40298c ("ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig") Signed-off-by: Tudor Ambarus --- configs/sama5d36ek_cmp_mmc_defconfig | 1 + configs/sama5d36ek_cmp_nandflash_defconfig | 1 + configs/sama5d36ek_cmp_spiflash_defconfig | 1 + configs/sama5d3_xplained_mmc_defconfig | 1 + configs/sama5d4ek_mmc_defconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index eb7eb80969..7b6cbb1e24 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -47,6 +47,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=4 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index ed78f4ed48..a3b2fac853 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_NAND_ATMEL=y +CONFIG_PMECC_CAP=4 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 556ea2f29e..4d604a2dea 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -49,6 +49,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=4 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 0aadf2a5c3..e35a575266 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -66,6 +66,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=4 CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 9c9862c1d5..3aa1fd4bdd 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ATMEL=y CONFIG_ATMEL_NAND_HW_PMECC=y +CONFIG_PMECC_CAP=8 CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_ATMEL=y From 786f888b743e9b83c9095cb9b5548ebe2e29afc5 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 8 Jan 2021 14:40:19 +0200 Subject: [PATCH 09/18] sama5d3: Fix Galois Field Table offsets Offsets are described in the datasheet at section: "11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction". For testing I "injected" bit flips into u-boot NAND memory area, and then read back. PMECC could not correct the errors. With the offsets updated everything is fine. Fixes: 3225f34e5c ("ARM: atmel: add sama5d3xek support") Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/include/mach/sama5d3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 83f18a8148..f4f05676f7 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -190,8 +190,8 @@ /* * PMECC table in ROM */ -#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000 -#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000 +#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 /* * SAMA5D3 specific prototypes From 3270c47b396ed8710f1135896d97c623cfe5a207 Mon Sep 17 00:00:00 2001 From: "Kai Stuhlemmer (ebee Engineering)" Date: Fri, 8 Jan 2021 14:40:20 +0200 Subject: [PATCH 10/18] sam9x60.h: Fix Galois Field Table offsets Because ATMEL_BASE_ROM is defined to 0x100000, it already points to the begin of the index table for 512 byte sectors correction. Thus its offset must be zero and the index of the table for 1024 byte sectors must start at offset 0x8000. Signed-off-by: Kai Stuhlemmer (ebee Engineering) [ta: update commit message] Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/include/mach/sam9x60.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h index b7f43226b7..c08d19c691 100644 --- a/arch/arm/mach-at91/include/mach/sam9x60.h +++ b/arch/arm/mach-at91/include/mach/sam9x60.h @@ -154,8 +154,8 @@ /* * PMECC table in ROM */ -#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 -#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 +#define ATMEL_PMECC_INDEX_OFFSET_512 0x0000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x8000 /* * SAM9X60 specific prototypes From bb890f75d5217a3c5db0fa40acf35ee317ec1905 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 19 Jan 2021 13:26:44 +0200 Subject: [PATCH 11/18] net: macb: add user io config data structure Different implementation of USER IO register needs different mapping for bit fields of this register. Add implementation for this and, since clken is part of USER IO and it needs to be activated based on per SoC capabilities, add caps in macb_config where clken specific information needs to be filled. Signed-off-by: Claudiu Beznea --- drivers/net/macb.c | 53 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 12 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 2225b33ff6..097d578710 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -144,11 +144,20 @@ struct macb_device { #endif }; +struct macb_usrio_cfg { + unsigned int mii; + unsigned int rmii; + unsigned int rgmii; + unsigned int clken; +}; + struct macb_config { unsigned int dma_burst_length; unsigned int hw_dma_cap; + unsigned int caps; int (*clk_init)(struct udevice *dev, ulong rate); + const struct macb_usrio_cfg *usrio; }; #ifndef CONFIG_DM_ETH @@ -850,6 +859,7 @@ static int _macb_init(struct macb_device *macb, const char *name) { #ifdef CONFIG_DM_ETH struct macb_device *macb = dev_get_priv(dev); + unsigned int val = 0; #endif unsigned long paddr; int ret; @@ -920,11 +930,17 @@ static int _macb_init(struct macb_device *macb, const char *name) * to select interface between RMII and MII. */ #ifdef CONFIG_DM_ETH - if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) || - (macb->phy_interface == PHY_INTERFACE_MODE_RGMII)) - gem_writel(macb, USRIO, GEM_BIT(RGMII)); - else - gem_writel(macb, USRIO, 0); + if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII) + val = macb->config->usrio->rgmii; + else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) + val = macb->config->usrio->rmii; + else if (macb->phy_interface == PHY_INTERFACE_MODE_MII) + val = macb->config->usrio->mii; + + if (macb->config->caps & MACB_CAPS_USRIO_HAS_CLKEN) + val |= macb->config->usrio->clken; + + gem_writel(macb, USRIO, val); if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) { unsigned int ncfgr = macb_readl(macb, NCFGR); @@ -934,7 +950,7 @@ static int _macb_init(struct macb_device *macb, const char *name) } #else #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) - gem_writel(macb, USRIO, GEM_BIT(RGMII)); + gem_writel(macb, USRIO, macb->config->usrio->rgmii); #else gem_writel(macb, USRIO, 0); #endif @@ -945,28 +961,30 @@ static int _macb_init(struct macb_device *macb, const char *name) #ifdef CONFIG_AT91FAMILY if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { macb_writel(macb, USRIO, - MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb->config->usrio->rmii | + macb->config->usrio->clken); } else { - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, macb->config->usrio->clken); } #else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) macb_writel(macb, USRIO, 0); else - macb_writel(macb, USRIO, MACB_BIT(MII)); + macb_writel(macb, USRIO, macb->config->usrio->mii); #endif #else #ifdef CONFIG_RMII #ifdef CONFIG_AT91FAMILY - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, macb->config->usrio->rmii | + macb->config->usrio->clken); #else macb_writel(macb, USRIO, 0); #endif #else #ifdef CONFIG_AT91FAMILY - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, macb->config->usrio->clken); #else - macb_writel(macb, USRIO, MACB_BIT(MII)); + macb_writel(macb, USRIO, macb->config->usrio->mii); #endif #endif /* CONFIG_RMII */ #endif @@ -1307,10 +1325,18 @@ static int macb_enable_clk(struct udevice *dev) } #endif +static const struct macb_usrio_cfg macb_default_usrio = { + .mii = MACB_BIT(MII), + .rmii = MACB_BIT(RMII), + .rgmii = GEM_BIT(RGMII), + .clken = MACB_BIT(CLKEN), +}; + static const struct macb_config default_gem_config = { .dma_burst_length = 16, .hw_dma_cap = HW_DMA_CAP_32B, .clk_init = NULL, + .usrio = &macb_default_usrio, }; static int macb_eth_probe(struct udevice *dev) @@ -1408,18 +1434,21 @@ static const struct macb_config microchip_config = { .dma_burst_length = 16, .hw_dma_cap = HW_DMA_CAP_64B, .clk_init = NULL, + .usrio = &macb_default_usrio, }; static const struct macb_config sama5d4_config = { .dma_burst_length = 4, .hw_dma_cap = HW_DMA_CAP_32B, .clk_init = NULL, + .usrio = &macb_default_usrio, }; static const struct macb_config sifive_config = { .dma_burst_length = 16, .hw_dma_cap = HW_DMA_CAP_32B, .clk_init = macb_sifive_clk_init, + .usrio = &macb_default_usrio, }; static const struct udevice_id macb_eth_ids[] = { From 96449581b3d57e3f1561cec82920a951664398b1 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 19 Jan 2021 13:26:45 +0200 Subject: [PATCH 12/18] net: macb: check clk_set_rate return value to be negative clk_set_rate() returns the set rate in case of success and a negative number in case of failure. Consider failure only the negative numbers. Fixes: 3ef64444de157 ("dm: net: macb: Implement link speed change callback") Signed-off-by: Claudiu Beznea --- drivers/net/macb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 097d578710..80ed58d4b9 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -631,7 +631,7 @@ int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed) if (tx_clk.dev) { ret = clk_set_rate(&tx_clk, rate); - if (ret) + if (ret < 0) return ret; } #endif From 8c0483ecbf6d251f2d12e9728ee142b29510fb4c Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 19 Jan 2021 13:26:46 +0200 Subject: [PATCH 13/18] net: macb: add support for sama7g5 gmac Add support for SAMA7G5 GMAC. Signed-off-by: Claudiu Beznea --- drivers/net/macb.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 80ed58d4b9..e87ffd9be3 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -595,6 +595,23 @@ static int macb_sifive_clk_init(struct udevice *dev, ulong rate) return 0; } +static int macb_sama7g5_clk_init(struct udevice *dev, ulong rate) +{ + struct clk clk; + int ret; + + ret = clk_get_by_name(dev, "tx_clk", &clk); + if (ret) + return ret; + + /* + * This is for using GCK. Clock rate is addressed via assigned-clock + * property, so only clock enable is needed here. The switching to + * proper clock rate depending on link speed is managed by IP logic. + */ + return clk_enable(&clk); +} + int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed) { #ifdef CONFIG_CLK @@ -1430,6 +1447,13 @@ static int macb_eth_of_to_plat(struct udevice *dev) return macb_late_eth_of_to_plat(dev); } +static const struct macb_usrio_cfg sama7g5_usrio = { + .mii = 0, + .rmii = 1, + .rgmii = 2, + .clken = BIT(2), +}; + static const struct macb_config microchip_config = { .dma_burst_length = 16, .hw_dma_cap = HW_DMA_CAP_64B, @@ -1451,10 +1475,19 @@ static const struct macb_config sifive_config = { .usrio = &macb_default_usrio, }; +static const struct macb_config sama7g5_gmac_config = { + .dma_burst_length = 16, + .hw_dma_cap = HW_DMA_CAP_32B, + .clk_init = macb_sama7g5_clk_init, + .usrio = &sama7g5_usrio, +}; + static const struct udevice_id macb_eth_ids[] = { { .compatible = "cdns,macb" }, { .compatible = "cdns,at91sam9260-macb" }, { .compatible = "cdns,sam9x60-macb" }, + { .compatible = "cdns,sama7g5-gem", + .data = (ulong)&sama7g5_gmac_config }, { .compatible = "atmel,sama5d2-gem" }, { .compatible = "atmel,sama5d3-gem" }, { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config }, From 3d3475c8b79567dabc0bf06f85119115fa849167 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 19 Jan 2021 13:26:47 +0200 Subject: [PATCH 14/18] net: macb: add support for sama7g5 emac Add support for SAMA7G5 EMAC. Signed-off-by: Claudiu Beznea --- drivers/net/macb.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index e87ffd9be3..f71331827c 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -1482,12 +1482,21 @@ static const struct macb_config sama7g5_gmac_config = { .usrio = &sama7g5_usrio, }; +static const struct macb_config sama7g5_emac_config = { + .caps = MACB_CAPS_USRIO_HAS_CLKEN, + .dma_burst_length = 16, + .hw_dma_cap = HW_DMA_CAP_32B, + .usrio = &sama7g5_usrio, +}; + static const struct udevice_id macb_eth_ids[] = { { .compatible = "cdns,macb" }, { .compatible = "cdns,at91sam9260-macb" }, { .compatible = "cdns,sam9x60-macb" }, { .compatible = "cdns,sama7g5-gem", .data = (ulong)&sama7g5_gmac_config }, + { .compatible = "cdns,sama7g5-emac", + .data = (ulong)&sama7g5_emac_config }, { .compatible = "atmel,sama5d2-gem" }, { .compatible = "atmel,sama5d3-gem" }, { .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config }, From 1ae8f0a3b2d882ca5b233cd482a50de523fdd182 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 19 Jan 2021 13:26:48 +0200 Subject: [PATCH 15/18] net: macb: take into account all RGMII interface types Take into account all RGMII interface types. Depending on it the RGMII PHY's timings are setup. Signed-off-by: Claudiu Beznea --- drivers/net/macb.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index f71331827c..6e26467700 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -947,7 +947,10 @@ static int _macb_init(struct macb_device *macb, const char *name) * to select interface between RMII and MII. */ #ifdef CONFIG_DM_ETH - if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII) + if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII || + macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || + macb->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) val = macb->config->usrio->rgmii; else if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) val = macb->config->usrio->rmii; From 911980059159392231d220aa13b0a05ad5b80869 Mon Sep 17 00:00:00 2001 From: Greg Gallagher Date: Thu, 21 Jan 2021 11:55:34 -0500 Subject: [PATCH 16/18] board: atmel: Add SAMA5D27 giant board Giant board is a tiny SBC based on the Adafruit Feather form factor, created by groboards it contains a SAMA5D2 processor (SAMA5D27), 128 MB of RAM and a microSD card for storage. Signed-off-by: Greg Gallagher --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/at91-sama5d27_giantboard.dts | 128 ++++++++++++++++++++++ board/atmel/sama5d27_som1_ek/MAINTAINERS | 6 + configs/sama5d27_giantboard_defconfig | 97 ++++++++++++++++ 4 files changed, 233 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/at91-sama5d27_giantboard.dts create mode 100644 configs/sama5d27_giantboard_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a9d36e0e9c..1d4eddd20e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -905,7 +905,8 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ at91-sama5d2_xplained.dtb dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ - at91-sama5d27_som1_ek.dtb + at91-sama5d27_som1_ek.dtb \ + at91-sama5d27_giantboard.dtb dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \ at91-sama5d27_wlsom1_ek.dtb diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts b/arch/arm/dts/at91-sama5d27_giantboard.dts new file mode 100644 index 0000000000..e81ca60ca0 --- /dev/null +++ b/arch/arm/dts/at91-sama5d27_giantboard.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * at91-sama5d27_giantboard.dts - Device Tree file for Giant Board + * + * Copyright (C) 2020 Greg Gallagher + * + * Derived from at91-sama5d27_som1_ek.dts + * + * Copyright (C) 2017 Microchip Corporation + * Wenyou Yang + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" + +/ { + model = "Giant Board"; + compatible = "atmel,sama5d27-giantboard", "atmel,sama5d2", "atmel,sama5"; + + memory { + reg = <0x20000000 0x8000000>; + }; + + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart1; + }; + + ahb { + sdmmc1: sdio-host@b0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + apb { + + uart1: serial@f8020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + i2c0: i2c@f8028000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + status = "okay"; + }; + + i2c1: i2c@fc028000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + pmic@5b { + compatible = "active-semi,act8945a"; + reg = <0x5b>; + active-semi,vsel-low; + status = "okay"; + }; + }; + + pit: timer@f8048030 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + + sfr: sfr@f8030000 { + status = "okay"; + u-boot,dm-pre-reloc; + }; + + pioA: gpio@fc038000 { + pinctrl { + + pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pinmux = , + , + , + , + ; + bias-pull-up; + u-boot,dm-pre-reloc; + }; + + pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + pinmux = , + ; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_uart1_default: uart1_default { + pinmux = , + ; + bias-disable; + u-boot,dm-pre-reloc; + }; + + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; + }; + }; + }; + }; +}; diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS index f2d2f49db3..ba2f31e6c4 100644 --- a/board/atmel/sama5d27_som1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -6,3 +6,9 @@ F: include/configs/sama5d27_som1_ek.h F: configs/sama5d27_som1_ek_mmc_defconfig F: configs/sama5d27_som1_ek_mmc1_defconfig F: configs/sama5d27_som1_ek_qspiflash_defconfig + +SAMA5D27 GIANT BOARD +M: Greg Gallagher +S: Maintained +F: configs/sama5d27_giantboard_defconfig +F: arch/arm/dts/at91-sama5d27_giantboard.dts diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig new file mode 100644 index 0000000000..4e55a62625 --- /dev/null +++ b/configs/sama5d27_giantboard_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_AT91=y +CONFIG_CMDLINE=y +CONFIG_SYS_TEXT_BASE=0x23f00000 +CONFIG_TARGET_SAMA5D27_SOM1_EK=y +CONFIG_SAMA5D27_GIANTBOARD=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf8020000 +CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SPL_FS_FAT=y +CONFIG_SYS_BOARD="giantboard" +CONFIG_SYS_BOARD_NAME="giantboard" +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_TEXT_BASE=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIBFDT=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_giantboard" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +# CONFIG_NET is not set +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_ATMEL_USBA=y From c69ba7b4a0878eaf9b6c1c2d9727888b93272141 Mon Sep 17 00:00:00 2001 From: Greg Gallagher Date: Thu, 21 Jan 2021 11:55:35 -0500 Subject: [PATCH 17/18] configs: sama5d27_som1_ek: Set FDT filename based on defconfig Make the FDT file name based on the default on that is specified in the defconfig file. Signed-off-by: Greg Gallagher --- include/configs/sama5d27_som1_ek.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 3358149e66..8942d15934 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -27,14 +27,11 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -/* NAND flash */ - -/* SPI flash */ - #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_SD_BOOT /* bootstrap + u-boot + env in sd card */ -#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d27_som1_ek.dtb; " \ +#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 " \ + CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \ "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ "bootz 0x22000000 - 0x21000000" #endif From 786f35b619ddbfb88e4532d11a56413f5dab473f Mon Sep 17 00:00:00 2001 From: Greg Gallagher Date: Thu, 21 Jan 2021 11:55:36 -0500 Subject: [PATCH 18/18] ARM: at91: spl: add spl_early_init for sama5d2 platforms The dm root node is needed early in the spl to allow the timer to be used. This change calls spl_early_init to initialize the dm root node. Signed-off-by: Greg Gallagher --- arch/arm/mach-at91/spl_atmel.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 23588e79f9..217ed12e31 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -103,6 +103,13 @@ void board_init_f(ulong dummy) { int ret; + if (IS_ENABLED(CONFIG_OF_CONTROL)) { + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + } switch_to_main_crystal_osc(); #ifdef CONFIG_SAMA5D2