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global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

Browse Source 
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini
2022-11-16 13:10:37 -05:00
parent aec118ebe6
commit aa6e94deab
589 changed files with 1197 additions and 1197 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/configs/10m50_devboard.h
View File

@@ -30,8 +30,8 @@
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
#define CONFIG_SYS_SDRAM_BASE 0xc8000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE 0xc8000000
#define CFG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#endif /* __CONFIG_H */

4
include/configs/3c120_devboard.h
View File

@@ -26,8 +26,8 @@
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
#define CONFIG_SYS_SDRAM_BASE 0xD0000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE 0xD0000000
#define CFG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#endif /* __CONFIG_H */

22
include/configs/M5208EVBE.h
View File

@@ -60,22 +60,22 @@
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1 0x43711630
#define CFG_SYS_SDRAM_CFG2 0x56670000
#define CFG_SYS_SDRAM_CTRL 0xE1002000
#define CFG_SYS_SDRAM_EMOD 0x80010000
#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#ifdef CONFIG_SYS_FLASH_CFI
@@ -100,8 +100,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \

12
include/configs/M5235EVB.h
View File

@@ -70,10 +70,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/*
* For booting Linux, the board info and command line data
@@ -81,7 +81,7 @@
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -109,8 +109,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DCM | \

12
include/configs/M5249EVB.h
View File

@@ -52,10 +52,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#if 0 /* test-only */
@@ -67,7 +67,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -90,8 +90,8 @@
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)

12
include/configs/M5253DEMO.h
View File

@@ -77,17 +77,17 @@
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
@@ -117,8 +117,8 @@
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(8) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)

12
include/configs/M5272C3.h
View File

@@ -71,10 +71,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
/*
@@ -82,7 +82,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*
* FLASH organization
@@ -100,8 +100,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \

12
include/configs/M5275EVB.h
View File

@@ -73,10 +73,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/*
@@ -84,7 +84,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -101,8 +101,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \

12
include/configs/M5282EVB.h
View File

@@ -72,10 +72,10 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
@@ -85,7 +85,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -105,8 +105,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \

22
include/configs/M53017EVB.h
View File

@@ -74,22 +74,22 @@
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1 0x43711630
#define CFG_SYS_SDRAM_CFG2 0x56670000
#define CFG_SYS_SDRAM_CTRL 0xE1092000
#define CFG_SYS_SDRAM_EMOD 0x80010000
#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -118,8 +118,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)

22
include/configs/M5329EVB.h
View File

@@ -68,22 +68,22 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x53722730
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1 0x53722730
#define CFG_SYS_SDRAM_CFG2 0x56670000
#define CFG_SYS_SDRAM_CTRL 0xE1092000
#define CFG_SYS_SDRAM_EMOD 0x40010000
#define CFG_SYS_SDRAM_MODE 0x018D0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -117,8 +117,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)

22
include/configs/M5373EVB.h
View File

@@ -70,22 +70,22 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x53722730
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1 0x53722730
#define CFG_SYS_SDRAM_CFG2 0x56670000
#define CFG_SYS_SDRAM_CTRL 0xE1092000
#define CFG_SYS_SDRAM_EMOD 0x40010000
#define CFG_SYS_SDRAM_MODE 0x018D0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
@@ -117,8 +117,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)

4
include/configs/MCR3000.h
View File

@@ -62,8 +62,8 @@
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
#define CFG_SYS_SDRAM_BASE 0x00000000
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE

4
include/configs/MPC837XERDB.h
View File

@@ -59,7 +59,7 @@
/*
* DDR Setup
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
@@ -69,7 +69,7 @@
/*
* Manually set up DDR parameters
*/
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ONLY_CURRENT \

2
include/configs/MPC8548CDS.h
View File

@@ -40,7 +40,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */

4
include/configs/P1010RDB.h
View File

@@ -110,9 +110,9 @@
#ifndef __ASSEMBLY__
extern unsigned long get_sdram_size(void);
#endif
#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR

4
include/configs/P2041RDB.h
View File

@@ -69,10 +69,10 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* Local Bus Definitions

2
include/configs/SBx81LIFKW.h
View File

@@ -7,7 +7,7 @@
#define _CONFIG_SBX81LIFKW_H
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration

2
include/configs/SBx81LIFXCAT.h
View File

@@ -7,7 +7,7 @@
#define _CONFIG_SBX81LIFXCAT_H
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration

6
include/configs/T102xRDB.h
View File

@@ -116,12 +116,12 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_SDRAM_SIZE 2048
#define CFG_SYS_SDRAM_SIZE 2048
#endif
/*

4
include/configs/T104xRDB.h
View File

@@ -88,11 +88,11 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions

4
include/configs/T208xQDS.h
View File

@@ -86,8 +86,8 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1

4
include/configs/T208xRDB.h
View File

@@ -81,8 +81,8 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1

4
include/configs/T4240RDB.h
View File

@@ -62,7 +62,7 @@
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
@@ -154,7 +154,7 @@
#define SPD_EEPROM_ADDRESS2 0x54
#define SPD_EEPROM_ADDRESS3 0x56
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions

2
include/configs/am62x_evm.h
View File

@@ -13,7 +13,7 @@
#include <environment/ti/mmc.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \

2
include/configs/am64x_evm.h
View File

@@ -16,7 +16,7 @@
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \

2
include/configs/am65x_evm.h
View File

@@ -15,7 +15,7 @@
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \

4
include/configs/amcore.h
View File

@@ -33,8 +33,8 @@
/* size of internal SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 0x1000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_FLASH_BASE 0xffc00000
/* amcore design has flash data bytes wired swapped */

2
include/configs/ap121.h
View File

@@ -6,7 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000

2
include/configs/ap143.h
View File

@@ -6,7 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000

2
include/configs/ap152.h
View File

@@ -6,7 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000

2
include/configs/apalis-imx8.h
View File

@@ -63,7 +63,7 @@
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */

2
include/configs/apalis_imx6.h
View File

@@ -106,7 +106,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

4
include/configs/arbel.h
View File

@@ -6,9 +6,9 @@
#ifndef __CONFIG_ARBEL_H
#define __CONFIG_ARBEL_H
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CFG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */

2
include/configs/aristainetos2.h
View File

@@ -406,7 +406,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/aspeed-common.h
View File

@@ -14,7 +14,7 @@
/* Misc CPU related */
#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ
#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)

12
include/configs/astro_mcf5373l.h
View File

@@ -57,7 +57,7 @@
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/*
* Define baudrate for UART1 (console output, tftp, ...)
@@ -158,7 +158,7 @@
* (Set up by the startup code)
* for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_BASE 0x40000000
/*
* Chipselect bank definitions
@@ -195,8 +195,8 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
(CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
(CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
@@ -213,8 +213,8 @@
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)

4
include/configs/at91sam9260ek.h
View File

@@ -31,8 +31,8 @@
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#ifdef CONFIG_AT91SAM9XE

4
include/configs/at91sam9261ek.h
View File

@@ -17,8 +17,8 @@
#include <asm/hardware.h>
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM

28
include/configs/at91sam9263ek.h
View File

@@ -23,8 +23,8 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
@@ -100,22 +100,22 @@
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \

4
include/configs/at91sam9m10g45ek.h
View File

@@ -15,8 +15,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x70000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE 0x70000000
#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND

4
include/configs/at91sam9n12ek.h
View File

@@ -14,8 +14,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE 0x08000000
/* DataFlash */

4
include/configs/at91sam9rlek.h
View File

@@ -17,8 +17,8 @@
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM

4
include/configs/at91sam9x5ek.h
View File

@@ -20,8 +20,8 @@
*/
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* DataFlash */

2
include/configs/ax25-ae350.h
View File

@@ -28,7 +28,7 @@
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0
/*
* Serial console configuration

4
include/configs/axs10x.h
View File

@@ -20,8 +20,8 @@
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_512M
#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_512M
/*
* UART configuration

2
include/configs/bcm947622.h
View File

@@ -6,7 +6,7 @@
#ifndef __BCM947622_H
#define __BCM947622_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define COUNTER_FREQUENCY 50000000
#endif

2
include/configs/bcm94908.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM94908_H
#define __BCM94908_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm94912.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM94912_H
#define __BCM94912_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm963138.h
View File

@@ -6,7 +6,7 @@
#ifndef __BCM963138_H
#define __BCM963138_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_HZ_CLOCK 500000000
#endif

2
include/configs/bcm963146.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM963146_H
#define __BCM963146_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm963148.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM963148_H
#define __BCM963148_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm963158.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM963158_H
#define __BCM963158_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm963178.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM963178_H
#define __BCM963178_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96756.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96756_H
#define __BCM96756_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96813.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96813_H
#define __BCM96813_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96846.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96846_H
#define __BCM96846_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96855.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96855_H
#define __BCM96855_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96856.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96856_H
#define __BCM96856_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96858.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96858_H
#define __BCM96858_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96878.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96878_H
#define __BCM96878_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm_ns3.h
View File

@@ -15,7 +15,7 @@
#define V2M_BASE 0x80000000
#define PHYS_SDRAM_1 V2M_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* Initial SP before reloaction is placed at end of first DRAM bank,

2
include/configs/bcmstb.h
View File

@@ -81,7 +81,7 @@ extern phys_addr_t prior_stage_fdt_address;
* MiB. However, BOLT can be configured to allow loading larger
* initramfs images, in which case this limitation is eliminated.
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
/*

4
include/configs/bitmain_antminer_s9.h
View File

@@ -6,8 +6,8 @@
#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H
#define __CONFIG_BITMAIN_ANTMINER_S9_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"pxefile_addr_r=0x2000000\0" \

2
include/configs/bk4r1.h
View File

@@ -199,7 +199,7 @@
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (SZ_512M)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/bmips_bcm3380.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm6318.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm63268.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm6328.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm6338.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm6348.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm6358.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm6362.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm6368.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

2
include/configs/bmips_bcm6838.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */

4
include/configs/boston.h
View File

@@ -22,9 +22,9 @@
* Memory map
*/
#ifdef CONFIG_64BIT
# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
# define CFG_SYS_SDRAM_BASE 0xffffffff80000000
#else
# define CONFIG_SYS_SDRAM_BASE 0x80000000
# define CFG_SYS_SDRAM_BASE 0x80000000
#endif
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000

2
include/configs/brppt2.h
View File

@@ -76,7 +76,7 @@ BUR_COMMON_ENV \
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/bur_am335x_common.h
View File

@@ -45,7 +45,7 @@
* always, even when we have more. We always start at 0x80000000,
* and we place the initial stack pointer in our SRAM.
*/
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/*
* Our platforms make use of SPL to initalize the hardware (primarily

2
include/configs/capricorn-common.h
View File

@@ -92,7 +92,7 @@
/* On CCP board, USDHC1 is for eMMC */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
/* DDR3 board total DDR is 1 GB */

2
include/configs/cgtqmx8.h
View File

@@ -111,7 +111,7 @@
#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */

2
include/configs/ci20.h
View File

@@ -11,7 +11,7 @@
/* Memory configuration */
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* NS16550-ish UARTs */

2
include/configs/cl-som-imx7.h
View File

@@ -82,7 +82,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/cm_fx6.h
View File

@@ -21,7 +21,7 @@
/* RAM */
#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

12
include/configs/cobra5272.h
View File

@@ -30,7 +30,7 @@
*/
#define CONFIG_SYS_CLK 66000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/* ---
* Define baudrate for UART1 (console output, tftp, ...)
@@ -152,9 +152,9 @@ enter a valid image address in flash */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
/*
*-------------------------------------------------------------------------
@@ -162,7 +162,7 @@ enter a valid image address in flash */
*-----------------------------------------------------------------------
*/
/* #define CONFIG_SYS_SDRAM_SIZE 16 */
/* #define CFG_SYS_SDRAM_SIZE 16 */
/*
*-----------------------------------------------------------------------
@@ -186,8 +186,8 @@ enter a valid image address in flash */
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \

2
include/configs/colibri-imx6ull.h
View File

@@ -116,7 +116,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/colibri-imx8x.h
View File

@@ -96,7 +96,7 @@
/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
#define CFG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */

2
include/configs/colibri_imx6.h
View File

@@ -100,7 +100,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/colibri_imx7.h
View File

@@ -160,7 +160,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/colibri_vf.h
View File

@@ -85,7 +85,7 @@
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (256 * SZ_1M)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/corstone1000.h
View File

@@ -22,7 +22,7 @@
#define PHYS_SDRAM_1 (V2M_BASE)
#define PHYS_SDRAM_1_SIZE 0x80000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0)

4
include/configs/corvus.h
View File

@@ -32,8 +32,8 @@
#define CONFIG_USART_ID ATMEL_ID_SYS
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6
#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND

2
include/configs/da850evm.h
View File

@@ -166,7 +166,7 @@
/* Load U-Boot Image From MMC */
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CFG_SYS_SDRAM_BASE 0xc0000000
#include <asm/arch/hardware.h>

2
include/configs/dart_6ul.h
View File

@@ -42,7 +42,7 @@
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_512M
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

4
include/configs/devkit3250.h
View File

@@ -15,8 +15,8 @@
/*
* Memory configurations
*/
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CFG_SYS_SDRAM_SIZE SZ_64M
/*
* DMA

2
include/configs/dh_imx6.h
View File

@@ -72,7 +72,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/display5.h
View File

@@ -283,7 +283,7 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE

2
include/configs/dragonboard410c.h
View File

@@ -17,7 +17,7 @@
#define PHYS_SDRAM_1 0x80000000
/* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */
#define PHYS_SDRAM_1_SIZE SZ_1G
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Environment */
#define BOOT_TARGET_DEVICES(func) \

2
include/configs/dragonboard820c.h
View File

@@ -19,7 +19,7 @@
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE 0x5ea4ffff
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#include <config_distro_bootcmd.h>

2
include/configs/durian.h
View File

@@ -11,7 +11,7 @@
/* Sdram Bank #1 Address */
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE 0x7B000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* BOOT */

2
include/configs/ea-lpc3250devkitv2.h
View File

@@ -13,7 +13,7 @@
/*
* RAM
*/
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
/*
* cmd

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