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global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

Browse Source 
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini
2022-11-16 13:10:37 -05:00
parent aec118ebe6
commit aa6e94deab
589 changed files with 1197 additions and 1197 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/ddr/fsl/arm_ddr_gen3.c
View File

@@ -130,7 +130,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */

2
drivers/ddr/fsl/fsl_ddr_gen4.c
View File

@@ -230,7 +230,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
if (is_warm_boot()) {
ddr_out32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */

2
drivers/ddr/fsl/main.c
View File

@@ -30,7 +30,7 @@
*/
#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
#ifdef CONFIG_MPC83xx
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE
#else
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif

2
drivers/ddr/fsl/mpc85xx_ddr_gen3.c
View File

@@ -162,7 +162,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
/* DRAM VRef will not be trained */

4
drivers/ddr/marvell/axp/ddr3_axp.h
View File

@@ -19,10 +19,10 @@
#define FAR_END_DIMM_ADDR 0x50
#define MAX_DIMM_ADDR 0x60
#ifndef CONFIG_SYS_SDRAM_SIZE
#ifndef CFG_SYS_SDRAM_SIZE
#define SDRAM_CS_SIZE 0xFFFFFFF
#else
#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1)
#define SDRAM_CS_SIZE ((CFG_SYS_SDRAM_SIZE >> 10) - 1)
#endif
#define SDRAM_CS_BASE 0x0
#define SDRAM_DIMM_SIZE 0x80000000

2
drivers/pci/Kconfig
View File

@@ -60,7 +60,7 @@ config PCI_MAP_SYSTEM_MEMORY
instead of a physical address (e.g. on MIPS). The PCI core will then remap
the virtual memory base address to a physical address when adding the PCI
region of type PCI_REGION_SYS_MEMORY.
This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still
being used as virtual address.
config PCI_SRIOV

4
drivers/pci/pci-rcar-gen2.c
View File

@@ -191,7 +191,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev)
/* AHB-PCI Bridge Communication Registers */
writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG);
writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16,
priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG);
writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16,
priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG);
@@ -204,7 +204,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev)
/* PCI Configuration Registers for AHBPCI */
devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0);
writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0);
writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
writel(CFG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1);
writel(0xf0000000, devad + PCI_BASE_ADDRESS_2);
writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_PARITY | PCI_COMMAND_SERR,

6
drivers/pci/pci_sh7751.c
View File

@@ -158,9 +158,9 @@ static int sh7751_pci_probe(struct udevice *dev)
/* Set up target memory mappings (for external DMA access) */
/* Map both P0 and P2 range to Area 3 RAM for ease of use */
p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
p4_out(0, SH7751_PCILSR1);
p4_out(0, SH7751_PCILAR1);

4
drivers/pci/pcie_dw_mvebu.c
View File

@@ -459,9 +459,9 @@ static void pcie_dw_set_host_bars(const void *regs_base)
}
/* Set the BAR base and size towards DDR */
bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
bar0 = CFG_SYS_SDRAM_BASE & ~0xf;
bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
reg = ((size >> 20) - 1) << 12;
writel(size, regs_base + RESIZABLE_BAR_CTL0);

4
drivers/pci/pcie_layerscape.h
View File

@@ -14,11 +14,11 @@
#include <asm/arch-ls102xa/svr.h>
#ifndef CFG_SYS_PCI_MEMORY_BUS
#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE
#endif
#ifndef CFG_SYS_PCI_MEMORY_PHYS
#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE
#endif
#ifndef CFG_SYS_PCI_MEMORY_SIZE

4
drivers/ram/aspeed/sdram_ast2500.c
View File

@@ -203,7 +203,7 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info)
u32 test_pattern = 0xdeadbeef;
u32 cap_param = SDRAM_CONF_CAP_1024M;
u32 refresh_timing_param = DDR4_TRFC;
const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
ram_size >>= 1) {
@@ -231,7 +231,7 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info)
((refresh_timing_param & SDRAM_AC_TRFC_MASK)
<< SDRAM_AC_TRFC_SHIFT));
info->info.base = CONFIG_SYS_SDRAM_BASE;
info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
clrsetbits_le32(&info->regs->config,
(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),

6
drivers/ram/aspeed/sdram_ast2600.c
View File

@@ -838,7 +838,7 @@ static void ast2600_sdrammc_calc_size(struct dram_info *info)
u32 test_pattern = 0xdeadbeef;
u32 cap_param = SDRAM_CONF_CAP_2048M;
u32 refresh_timing_param = DDR4_TRFC;
const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset;
for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
ram_size >>= 1) {
@@ -866,7 +866,7 @@ static void ast2600_sdrammc_calc_size(struct dram_info *info)
((refresh_timing_param & SDRAM_AC_TRFC_MASK)
<< SDRAM_AC_TRFC_SHIFT));
info->info.base = CONFIG_SYS_SDRAM_BASE;
info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK,
@@ -1015,7 +1015,7 @@ static void ast2600_sdrammc_update_size(struct dram_info *info)
break;
}
info->info.base = CONFIG_SYS_SDRAM_BASE;
info->info.base = CFG_SYS_SDRAM_BASE;
info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info);
if (0 == (conf & SDRAM_CONF_ECC_SETUP))

12
drivers/ram/mediatek/ddr3-mt7629.c
View File

@@ -243,17 +243,17 @@ static int mtk_ddr3_rank_size_detect(struct udevice *dev)
* and it has maximum addressing region
*/
writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE);
writel(WALKING_PATTERN, CFG_SYS_SDRAM_BASE);
if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN)
if (readl(CFG_SYS_SDRAM_BASE) != WALKING_PATTERN)
return -EINVAL;
for (step = 0; step < 5; step++) {
writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE +
writel(~WALKING_PATTERN, CFG_SYS_SDRAM_BASE +
(WALKING_STEP << step));
start = readl(CONFIG_SYS_SDRAM_BASE);
test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step));
start = readl(CFG_SYS_SDRAM_BASE);
test = readl(CFG_SYS_SDRAM_BASE + (WALKING_STEP << step));
if ((test != ~WALKING_PATTERN) || test == start)
break;
}
@@ -727,7 +727,7 @@ static int mtk_ddr3_get_info(struct udevice *dev, struct ram_info *info)
struct mtk_ddr3_priv *priv = dev_get_priv(dev);
u32 val = readl(priv->emi + EMI_CONA);
info->base = CONFIG_SYS_SDRAM_BASE;
info->base = CFG_SYS_SDRAM_BASE;
switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) {
case 0:

2
drivers/ram/octeon/octeon_ddr.c
View File

@@ -2687,7 +2687,7 @@ static int octeon_ddr_probe(struct udevice *dev)
if (!mem_mbytes)
return -ENODEV;
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = MB(mem_mbytes);
/*

12
drivers/ram/rockchip/dmc-rk3368.c
View File

@@ -617,12 +617,12 @@ static int sdram_col_row_detect(struct udevice *dev)
/* Detect col */
for (col = 11; col >= 9; col--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE +
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE +
(1 << (col + params->chan.bw - 1));
writel(test_pattern, addr);
if ((readl(addr) == test_pattern) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
@@ -637,11 +637,11 @@ static int sdram_col_row_detect(struct udevice *dev)
/* Detect row*/
for (row = 16; row >= 12; row--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(test_pattern, addr);
if ((readl(addr) == test_pattern) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}

34
drivers/ram/rockchip/sdram_common.c
View File

@@ -220,12 +220,12 @@ int sdram_detect_col(struct sdram_cap_info *cap_info,
u32 bw = cap_info->bw;
for (col = coltmp; col >= 9; col -= 1) {
writel(0, CONFIG_SYS_SDRAM_BASE);
test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
writel(0, CFG_SYS_SDRAM_BASE);
test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (col + bw - 1ul)));
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -245,12 +245,12 @@ int sdram_detect_bank(struct sdram_cap_info *cap_info,
u32 bk;
u32 bw = cap_info->bw;
test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (coltmp + bktmp + bw - 1ul)));
writel(0, CONFIG_SYS_SDRAM_BASE);
writel(0, CFG_SYS_SDRAM_BASE);
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
bk = 3;
else
bk = 2;
@@ -268,12 +268,12 @@ int sdram_detect_bg(struct sdram_cap_info *cap_info,
u32 dbw;
u32 bw = cap_info->bw;
test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (coltmp + bw + 1ul)));
writel(0, CONFIG_SYS_SDRAM_BASE);
writel(0, CFG_SYS_SDRAM_BASE);
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
dbw = 0;
else
dbw = 1;
@@ -337,12 +337,12 @@ int sdram_detect_row(struct sdram_cap_info *cap_info,
void __iomem *test_addr;
for (row = rowtmp; row > 12; row--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
writel(0, CFG_SYS_SDRAM_BASE);
test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(1ul << (row + bktmp + coltmp + bw - 1ul)));
writel(PATTERN, test_addr);
if ((readl(test_addr) == PATTERN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
@@ -363,8 +363,8 @@ int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
u32 row = cap_info->cs0_row;
void __iomem *test_addr, *test_addr1;
test_addr = CONFIG_SYS_SDRAM_BASE;
test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
test_addr = CFG_SYS_SDRAM_BASE;
test_addr1 = (void __iomem *)(CFG_SYS_SDRAM_BASE +
(0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
writel(0, test_addr);
@@ -421,15 +421,15 @@ int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type)
/* detect cs1 row */
for (row = cap_info->cs0_row; row > 12; row--) {
test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
cs0_cap +
(1ul << (row + bktmp + coltmp + bw - 1ul)));
writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap);
writel(0, CFG_SYS_SDRAM_BASE + cs0_cap);
writel(PATTERN, test_addr);
if (((readl(test_addr) & byte_mask) ==
(PATTERN & byte_mask)) &&
((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) &
((readl(CFG_SYS_SDRAM_BASE + cs0_cap) &
byte_mask) == 0)) {
break;
}

2
drivers/ram/rockchip/sdram_px30.c
View File

@@ -726,7 +726,7 @@ static int px30_dmc_probe(struct udevice *dev)
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: grf=%p\n", __func__, priv->pmugrf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);

14
drivers/ram/rockchip/sdram_rk3066.c
View File

@@ -616,12 +616,12 @@ static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, in
/* Detect col. */
for (col = 11; col >= 9; col--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE +
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTERN, addr);
if ((readl(addr) == TEST_PATTERN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -638,11 +638,11 @@ static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, in
rk3066_dmc_move_to_access_state(chan);
/* Detect row, max 15, min13 for rk3066 */
for (row = 16; row >= 13; row--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTERN, addr);
if ((readl(addr) == TEST_PATTERN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
@@ -854,7 +854,7 @@ static int rk3066_dmc_probe(struct udevice *dev)
if (ret)
return ret;
} else {
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]);
}

2
drivers/ram/rockchip/sdram_rk3128.c
View File

@@ -23,7 +23,7 @@ static int rk3128_dmc_probe(struct udevice *dev)
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
debug("%s: grf=%p\n", __func__, priv->grf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[1]);

14
drivers/ram/rockchip/sdram_rk3188.c
View File

@@ -638,12 +638,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel,
/* Detect col */
for (col = 11; col >= 9; col--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE +
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -660,11 +660,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel,
move_to_access_state(chan);
/* Detect row, max 15,min13 in rk3188*/
for (row = 16; row >= 13; row--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
@@ -919,7 +919,7 @@ static int rk3188_dmc_probe(struct udevice *dev)
if (ret)
return ret;
#else
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmu->sys_reg[2]);
#endif

24
drivers/ram/rockchip/sdram_rk322x.c
View File

@@ -636,12 +636,12 @@ static int dram_cap_detect(struct dram_info *dram,
writel(3, &axi_bus->ddrconf);
move_to_access_state(dram->chan[0].pctl);
for (col = 11; col >= 9; col--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE +
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE +
(1 << (col + bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -656,11 +656,11 @@ static int dram_cap_detect(struct dram_info *dram,
/* Detect row*/
for (row = 16; row >= 12; row--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 11) {
@@ -672,11 +672,11 @@ static int dram_cap_detect(struct dram_info *dram,
sdram_params->ch[0].cs0_row = row;
}
/* cs detect */
writel(0, CONFIG_SYS_SDRAM_BASE);
writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30));
writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4);
if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
writel(0, CFG_SYS_SDRAM_BASE);
writel(TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30));
writel(~TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4);
if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
(readl(CFG_SYS_SDRAM_BASE) == 0))
sdram_params->ch[0].rank = 2;
else
sdram_params->ch[0].rank = 1;
@@ -813,7 +813,7 @@ static int rk322x_dmc_probe(struct udevice *dev)
if (ret)
return ret;
#else
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[2]);
#endif

14
drivers/ram/rockchip/sdram_rk3288.c
View File

@@ -684,12 +684,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel,
/* Detect col */
for (col = 11; col >= 9; col--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE +
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
@@ -705,11 +705,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel,
move_to_access_state(chan);
/* Detect row*/
for (row = 16; row >= 12; row--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(0, CFG_SYS_SDRAM_BASE);
addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTEN, addr);
if ((readl(addr) == TEST_PATTEN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
(readl(CFG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 11) {
@@ -1087,7 +1087,7 @@ static int rk3288_dmc_probe(struct udevice *dev)
if (ret)
return ret;
#else
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmu->sys_reg[2]);
#endif

2
drivers/ram/rockchip/sdram_rk3308.c
View File

@@ -21,7 +21,7 @@ static int rk3308_dmc_probe(struct udevice *dev)
struct dram_info *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2);
return 0;

2
drivers/ram/rockchip/sdram_rk3328.c
View File

@@ -580,7 +580,7 @@ static int rk3328_dmc_probe(struct udevice *dev)
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
debug("%s: grf=%p\n", __func__, priv->grf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->grf->os_reg[2]);
#endif

2
drivers/ram/rockchip/sdram_rk3399.c
View File

@@ -3151,7 +3151,7 @@ static int rk3399_dmc_probe(struct udevice *dev)
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
#endif

2
drivers/ram/rockchip/sdram_rk3568.c
View File

@@ -21,7 +21,7 @@ static int rk3568_dmc_probe(struct udevice *dev)
struct dram_info *priv = dev_get_priv(dev);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);

4
drivers/usb/host/ehci-rmobile.c
View File

@@ -90,7 +90,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
/* AHB-PCI Bridge Communication Registers */
writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
&ahbcom_pci->pciahb_win1_ctr);
writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
&ahbcom_pci->pciahb_win2_ctr);
@@ -103,7 +103,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
&ahbcom_pci->ahbpci_win1_ctr);
writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
writel(0xf0000000, &ahbconf_pci->win2_basead);
writel(SERREN | PERREN | MASTEREN | MEMEN,
&ahbconf_pci->cmnd_sts);

4
drivers/video/sunxi/sunxi_display.c
View File

@@ -385,7 +385,7 @@ static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
(struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);
writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
writel(CFG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
writel(mode->xres * 4, &de_fe->ch0_stride);
writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt);
writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt);
@@ -1222,7 +1222,7 @@ static int sunxi_de_probe(struct udevice *dev)
EFI_RESERVED_MEMORY_TYPE);
#endif
fb_dma_addr = sunxi_display->fb_addr - CONFIG_SYS_SDRAM_BASE;
fb_dma_addr = sunxi_display->fb_addr - CFG_SYS_SDRAM_BASE;
if (overscan_offset) {
fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
sunxi_display->fb_addr += ALIGN(overscan_offset, 0x1000);