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global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

Browse Source 
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini
2022-11-16 13:10:37 -05:00
parent aec118ebe6
commit aa6e94deab
589 changed files with 1197 additions and 1197 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/BuR/brppt1/board.c
View File

@@ -150,7 +150,7 @@ int board_init(void)
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

20
board/BuS/eb_cpu5282/eb_cpu5282.c
View File

@@ -40,8 +40,8 @@ int dram_init(void)
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
asm (" nop");
#ifdef CONFIG_SYS_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
#ifdef CFG_SYS_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)|
MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
MCFSDRAMC_DACR_PS_32;
asm (" nop");
@@ -54,7 +54,7 @@ int dram_init(void)
for (i = 0; i < 10; i++)
asm (" nop");
*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
*(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
asm (" nop");
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
asm (" nop");
@@ -65,12 +65,12 @@ int dram_init(void)
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
asm (" nop");
/* write SDRAM mode register */
*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
*(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
asm (" nop");
size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024;
#endif
#ifdef CONFIG_SYS_SDRAM_BASE1xx
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
#ifdef CFG_SYS_SDRAM_BASE1xx
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
@@ -79,15 +79,15 @@ int dram_init(void)
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
*(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
*(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
gd->ram_size = size;

2
board/CZ.NIC/turris_mox/turris_mox.c
View File

@@ -139,7 +139,7 @@ int board_fix_fdt(void *blob)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/Marvell/mvebu_alleycat-5/board.c
View File

@@ -7,7 +7,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/Marvell/mvebu_armada-37xx/board.c
View File

@@ -80,7 +80,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/Marvell/mvebu_armada-8k/board.c
View File

@@ -150,7 +150,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/Marvell/octeontx/board.c
View File

@@ -63,7 +63,7 @@ int timer_init(void)
int dram_init(void)
{
gd->ram_size = smc_dram_size(0);
gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
gd->ram_size -= CFG_SYS_SDRAM_BASE;
mem_map_fill();
return 0;

2
board/Marvell/octeontx2/board.c
View File

@@ -105,7 +105,7 @@ int timer_init(void)
int dram_init(void)
{
gd->ram_size = smc_dram_size(0);
gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
gd->ram_size -= CFG_SYS_SDRAM_BASE;
mem_map_fill();

2
board/Marvell/octeontx2_cn913x/board.c
View File

@@ -34,7 +34,7 @@ int board_early_init_r(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

6
board/armltd/integrator/integrator.c
View File

@@ -137,7 +137,7 @@ int misc_init_r (void)
int dram_init (void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
#ifdef CONFIG_CM_SPD_DETECT
{
extern void dram_query(void);
@@ -160,12 +160,12 @@ extern void dram_query(void);
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
REMAPPED_FLASH_SZ,
0x01000000 << sdram_shift);
}
#else
gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
REMAPPED_FLASH_SZ,
PHYS_SDRAM_1_SIZE);
#endif /* CM_SPD_DETECT */

2
board/armltd/vexpress/vexpress_common.c
View File

@@ -73,7 +73,7 @@ static void flash__init(void)
int dram_init(void)
{
gd->ram_size =
get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
get_ram_size((long *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
return 0;
}

12
board/astro/mcf5373l/mcf5373l.c
View File

@@ -39,12 +39,12 @@ int dram_init(void)
* GPIO configuration for bus should be set correctly from reset,
* so we do not care! First, set up address space: at this point,
* we should be running from internal SRAM;
* so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
* so use CFG_SYS_SDRAM_BASE as the base address for SDRAM,
* and do not care where it is
*/
__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
__raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
&sdp->cs0);
__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
__raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
&sdp->cs1);
/*
* I am not sure from the data sheet, but it seems burst length
@@ -72,7 +72,7 @@ int dram_init(void)
*/
__raw_writel(0x71462C00, &sdp->ctrl);
/* Dummy write to start SDRAM */
writel(0, CONFIG_SYS_SDRAM_BASE);
writel(0, CFG_SYS_SDRAM_BASE);
#endif
/*
@@ -82,8 +82,8 @@ int dram_init(void)
* (Do not rely on the SDCS register(s) being set to 0x00000000
* during reset as stated in the data sheet.)
*/
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
0x80000000 - CONFIG_SYS_SDRAM_BASE);
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
0x80000000 - CFG_SYS_SDRAM_BASE);
return 0;
}

6
board/atmel/at91sam9260ek/at91sam9260ek.c
View File

@@ -81,7 +81,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9260ek_nand_hw_init();
@@ -92,8 +92,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
(void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/at91sam9261ek/at91sam9261ek.c
View File

@@ -156,7 +156,7 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init();
@@ -176,8 +176,8 @@ int board_eth_init(struct bd_info *bis)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/at91sam9263ek/at91sam9263ek.c
View File

@@ -95,7 +95,7 @@ int board_init(void)
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init();
@@ -108,8 +108,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
View File

@@ -168,7 +168,7 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9m10g45ek_nand_hw_init();
@@ -181,8 +181,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/at91sam9n12ek/at91sam9n12ek.c
View File

@@ -99,7 +99,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
at91sam9n12ek_nand_hw_init();
@@ -114,8 +114,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/at91sam9rlek/at91sam9rlek.c
View File

@@ -93,7 +93,7 @@ int board_init(void)
/* arch number of AT91SAM9RLEK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9rlek_nand_hw_init();
@@ -104,7 +104,7 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
(void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/at91sam9x5ek/at91sam9x5ek.c
View File

@@ -115,7 +115,7 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
at91sam9x5ek_nand_hw_init();
@@ -129,8 +129,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sam9x60ek/sam9x60ek.c
View File

@@ -120,7 +120,7 @@ int misc_init_r(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
sam9x60ek_nand_hw_init();
@@ -130,7 +130,7 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c
View File

@@ -65,7 +65,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -84,8 +84,8 @@ int misc_init_r(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sama5d2_icp/sama5d2_icp.c
View File

@@ -54,7 +54,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -63,8 +63,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c
View File

@@ -115,7 +115,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
rgb_leds_init();
@@ -130,8 +130,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sama5d3_xplained/sama5d3_xplained.c
View File

@@ -94,7 +94,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d3_xplained_nand_hw_init();
@@ -110,8 +110,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sama5d3xek/sama5d3xek.c
View File

@@ -147,7 +147,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d3xek_nand_hw_init();
@@ -166,8 +166,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sama5d4_xplained/sama5d4_xplained.c
View File

@@ -121,7 +121,7 @@ int misc_init_r(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d4_xplained_nand_hw_init();
@@ -135,8 +135,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sama5d4ek/sama5d4ek.c
View File

@@ -107,7 +107,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND_ATMEL
sama5d4ek_nand_hw_init();
@@ -121,8 +121,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/atmel/sama7g5ek/sama7g5ek.c
View File

@@ -67,7 +67,7 @@ int misc_init_r(void)
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
board_leds_init();
@@ -76,7 +76,7 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/bluewater/gurnard/gurnard.c
View File

@@ -307,7 +307,7 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
ret = gurnard_nand_hw_init();
@@ -407,8 +407,8 @@ int board_eth_init(struct bd_info *bis)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

2
board/bosch/guardian/board.c
View File

@@ -182,7 +182,7 @@ int board_init(void)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_MTD_RAW_NAND
gpmc_init();

2
board/bosch/shc/board.c
View File

@@ -449,7 +449,7 @@ int board_init(void)
if (read_eeprom() < 0)
puts("EEPROM Content Invalid.\n");
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif

8
board/broadcom/bcm_ep/board.c
View File

@@ -26,7 +26,7 @@ int board_init(void)
* Address of boot parameters passed to kernel
* Use default offset 0x100
*/
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
@@ -36,14 +36,14 @@ int board_init(void)
*/
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;

6
board/calao/usb_a9263/usb_a9263.c
View File

@@ -95,7 +95,7 @@ static void usb_a9263_macb_hw_init(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
usb_a9263_nand_hw_init();
@@ -111,8 +111,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

2
board/cobra5272/cobra5272.c
View File

@@ -28,7 +28,7 @@ int dram_init(void)
/* Dummy write to start SDRAM */
*((volatile unsigned long *) 0) = 0;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};

2
board/compulab/cm_t43/cm_t43.c
View File

@@ -45,7 +45,7 @@ int power_init_board(void)
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
set_i2c_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

4
board/compulab/cm_t43/spl.c
View File

@@ -119,7 +119,7 @@ void sdram_init(void)
unsigned long ram_size;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000);
if (ram_size == 0x80000000 ||
ram_size == 0x40000000 ||
ram_size == 0x20000000)
@@ -127,7 +127,7 @@ void sdram_init(void)
ddr3_emif_regs.sdram_config = 0x638453B2;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000);
if (ram_size == 0x08000000)
return;

2
board/cssi/MCR3000/MCR3000.c
View File

@@ -114,7 +114,7 @@ int dram_init(void)
out_be32(&memctl->memc_mcr, 0x80002038);
udelay(200);
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
SDRAM_MAX_SIZE);
return 0;

4
board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
View File

@@ -29,13 +29,13 @@ board_early_init_f(void)
int
board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x2000;
return 0;
}
int
dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_64M);
return 0;
}

2
board/eets/pdu001/board.c
View File

@@ -286,7 +286,7 @@ int board_init(void)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

6
board/egnite/ethernut5/ethernut5.c
View File

@@ -85,8 +85,8 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
(void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}
@@ -135,7 +135,7 @@ int board_init(void)
at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Set adress of boot parameters. */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Initialize UARTs and power management. */
ethernut5_power_init();
#ifdef CONFIG_CMD_NAND

2
board/emulation/qemu-arm/qemu-arm.c
View File

@@ -126,7 +126,7 @@ void *board_fdt_blob_setup(int *err)
{
*err = 0;
/* QEMU loads a generated DTB for us at the start of RAM. */
return (void *)CONFIG_SYS_SDRAM_BASE;
return (void *)CFG_SYS_SDRAM_BASE;
}
void enable_caches(void)

2
board/esd/meesc/meesc.c
View File

@@ -264,7 +264,7 @@ int board_init(void)
meesc_ethercat_hw_init();
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
meesc_nand_hw_init();

2
board/freescale/common/arm_sleep.c
View File

@@ -61,7 +61,7 @@ static void dp_ddr_restore(void)
/* get the address of ddr date from SPARECR3 */
src = (u64 *)in_le32(&scfg->sparecr[2]);
dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
dst = (u64 *)CFG_SYS_SDRAM_BASE;
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst++ = *src++;

2
board/freescale/common/mpc85xx_sleep.c
View File

@@ -50,7 +50,7 @@ static void dp_ddr_restore(void)
/* get the address of ddr date from SPARECR3 */
src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
for (i = 0; i < DDR_BUFF_LEN / 8; i++)
*dst-- = *src--;

4
board/freescale/ls1012afrdm/ls1012afrdm.c
View File

@@ -102,7 +102,7 @@ int dram_init(void)
else
gd->ram_size = SYS_SDRAM_SIZE_512;
#else
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = CFG_SYS_SDRAM_SIZE;
#endif
}
return 0;
@@ -139,7 +139,7 @@ int dram_init(void)
gd->ram_size = SYS_SDRAM_SIZE_512;
}
#else
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = CFG_SYS_SDRAM_SIZE;
#endif
mmdc_init(&mparam);

4
board/freescale/ls1012aqds/ls1012aqds.c
View File

@@ -66,7 +66,7 @@ int dram_init(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -90,7 +90,7 @@ int dram_init(void)
};
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = CFG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();

4
board/freescale/ls1012ardb/ls1012ardb.c
View File

@@ -113,7 +113,7 @@ int dram_init(void)
{
gd->ram_size = tfa_get_dram_size();
if (!gd->ram_size)
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -140,7 +140,7 @@ int dram_init(void)
mmdc_init(&mparam);
#endif
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = CFG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();

2
board/freescale/ls1021aqds/ddr.c
View File

@@ -192,7 +192,7 @@ int fsl_initdram(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;

2
board/freescale/ls1021atsn/ls1021atsn.c
View File

@@ -47,7 +47,7 @@ static void ddrmc_init(void)
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */

2
board/freescale/ls1021atwr/ls1021atwr.c
View File

@@ -162,7 +162,7 @@ void ddrmc_init(void)
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */

26
board/freescale/m5208evbe/m5208evbe.c
View File

@@ -29,7 +29,7 @@ int dram_init(void)
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,35 +37,35 @@ int dram_init(void)
}
i--;
out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
#ifdef CFG_SYS_SDRAM_BASE1
out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
#endif
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
asm("nop");
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
asm("nop");
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
(CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
asm("nop");
udelay(100);

8
board/freescale/m5235evb/m5235evb.c
View File

@@ -44,7 +44,7 @@ int dram_init(void)
GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
GPIO_PAR_SDRAM_SDCS(3));
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -61,7 +61,7 @@ int dram_init(void)
/* Initialize DACR0 */
out_be32(&sdram->dacr0,
SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) |
SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
SDRAMC_DARCn_PS_32);
asm("nop");
@@ -80,7 +80,7 @@ int dram_init(void)
}
/* Write to this block to initiate precharge */
*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
*(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
@@ -95,7 +95,7 @@ int dram_init(void)
asm("nop");
/* Write to the SDRAM Mode Register */
*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
*(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
gd->ram_size = dramsize;

2
board/freescale/m5249evb/m5249evb.c
View File

@@ -86,7 +86,7 @@ int dram_init(void)
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};

6
board/freescale/m5253demo/m5253demo.c
View File

@@ -47,7 +47,7 @@ int dram_init(void)
__asm__("nop");
/* Initialize DMR0 */
dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
dramsize = (CFG_SYS_SDRAM_SIZE << 20);
temp = (dramsize - 1) & 0xFFFC0000;
mbar_writeLong(MCFSIM_DMR0, temp | 1);
__asm__("nop");
@@ -57,7 +57,7 @@ int dram_init(void)
__asm__("nop");
/* Write to this block to initiate precharge */
*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
*(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
mb();
__asm__("nop");
@@ -74,7 +74,7 @@ int dram_init(void)
mbar_readLong(MCFSIM_DACR0) | 0x0040);
__asm__("nop");
*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
*(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
mb();
}

2
board/freescale/m5272c3/m5272c3.c
View File

@@ -30,7 +30,7 @@ int dram_init(void)
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};

18
board/freescale/m5275evb/m5275evb.c
View File

@@ -35,7 +35,7 @@ int dram_init(void)
out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */
out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE);
out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */
@@ -49,34 +49,34 @@ int dram_init(void)
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
setbits_be32(&sdp->sdmr,
MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
MCF_SDRAMC_SDMR_CMD);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
out_be32(&sdp->sdmr, 0x058d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
out_be32(&sdp->sdmr, 0x018d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
@@ -91,7 +91,7 @@ int dram_init(void)
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3));
gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
return 0;
};

8
board/freescale/m5282evb/m5282evb.c
View File

@@ -21,7 +21,7 @@ int dram_init(void)
{
u32 dramsize, i, dramclk;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -40,7 +40,7 @@ int dram_init(void)
/* Initialize DACR0 */
MCFSDRAMC_DACR0 = (0
| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
| MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_32);
@@ -62,7 +62,7 @@ int dram_init(void)
}
/* Write to this block to initiate precharge */
*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
*(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696;
asm("nop");
/* Set RE (bit 15) in DACR */
@@ -79,7 +79,7 @@ int dram_init(void)
asm("nop");
/* Write to the SDRAM Mode Register */
*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
*(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
gd->ram_size = dramsize;

2
board/freescale/m53017evb/README
View File

@@ -106,7 +106,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================

26
board/freescale/m53017evb/m53017evb.c
View File

@@ -29,7 +29,7 @@ int dram_init(void)
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,35 +37,35 @@ int dram_init(void)
}
i--;
out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
#ifdef CFG_SYS_SDRAM_BASE1
out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i);
#endif
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
asm("nop");
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
asm("nop");
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
asm("nop");
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
(CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);

24
board/freescale/m5329evb/m5329evb.c
View File

@@ -29,7 +29,7 @@ int dram_init(void)
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,30 +37,30 @@ int dram_init(void)
}
i--;
out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
(CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);

2
board/freescale/m5373evb/README
View File

@@ -105,7 +105,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
CFG_SYS_SDRAM_BASE -- defines the DRAM Base
2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
===========================================

24
board/freescale/m5373evb/m5373evb.c
View File

@@ -29,7 +29,7 @@ int dram_init(void)
sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
@@ -37,30 +37,30 @@ int dram_init(void)
}
i--;
out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i);
out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1);
out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD);
out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4);
out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE);
out_be32(&sdram->ctrl,
(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
(CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);

6
board/freescale/mpc837xerdb/mpc837xerdb.c
View File

@@ -97,10 +97,10 @@ int dram_init(void)
int fixed_sdram(void)
{
immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = CONFIG_SYS_SDRAM_SIZE;
u32 msize = CFG_SYS_SDRAM_SIZE;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
@@ -127,7 +127,7 @@ int fixed_sdram(void)
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
udelay(2000);
return CONFIG_SYS_SDRAM_SIZE >> 20;
return CFG_SYS_SDRAM_SIZE >> 20;
}
#endif /*!CONFIG_SYS_SPD_EEPROM */

2
board/freescale/mx51evk/mx51evk.c
View File

@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}

2
board/freescale/p1_p2_rdb_pc/ddr.c
View File

@@ -244,7 +244,7 @@ phys_size_t fixed_sdram(void)
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freq_ddrbus));
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);

8
board/friendlyarm/nanopi2/board.c
View File

@@ -507,7 +507,7 @@ int splash_screen_prepare(void)
/* u-boot dram initialize */
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}
@@ -518,10 +518,10 @@ int dram_init_banksize(void)
unsigned int reg_val = readl(SCR_USER_SIG6_READ);
/* set global data memory */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x00000100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100;
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;
/* Number of Row: 14 bits */
if ((reg_val >> 28) == 14)

6
board/gardena/smart-gateway-at91sam/board.c
View File

@@ -45,15 +45,15 @@ int board_early_init_f(void)
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

6
board/gdsys/mpc8308/sdram.c
View File

@@ -34,11 +34,11 @@ DECLARE_GLOBAL_DATA_PTR;
static long fixed_sdram(void)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = CONFIG_SYS_SDRAM_SIZE;
u32 msize = CFG_SYS_SDRAM_SIZE;
u32 msize_log2 = __ilog2(msize);
out_be32(&im->sysconf.ddrlaw[0].bar,
CONFIG_SYS_SDRAM_BASE & 0xfffff000);
CFG_SYS_SDRAM_BASE & 0xfffff000);
out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
@@ -66,7 +66,7 @@ static long fixed_sdram(void)
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
sync();
return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
return get_ram_size(CFG_SYS_SDRAM_BASE, msize);
}
int dram_init(void)

2
board/grinn/chiliboard/board.c
View File

@@ -95,7 +95,7 @@ int board_init(void)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
return 0;

2
board/imgtec/boston/ddr.c
View File

@@ -27,7 +27,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size)
{
DECLARE_GLOBAL_DATA_PTR;
if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
if (gd->ram_top < CFG_SYS_SDRAM_BASE) {
/* 2GB wrapped around to 0 */
return CKSEG0ADDR(256 << 20);
}

4
board/imgtec/malta/lowlevel_init.S
View File

@@ -118,7 +118,7 @@ _msc01:
/* setup basic address decode */
PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
li t1, 0x0
li t2, -CONFIG_SYS_SDRAM_SIZE
li t2, -CFG_SYS_SDRAM_SIZE
sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
@@ -168,7 +168,7 @@ _msc01:
sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
/* setup PCI_BAR0 memory window */
li t1, -CONFIG_SYS_SDRAM_SIZE
li t1, -CFG_SYS_SDRAM_SIZE
sw t1, MSC01_PCI_BAR0_OFS(t0)
/* setup PCI to SysCon/CPU translation */

2
board/imgtec/malta/malta.c
View File

@@ -94,7 +94,7 @@ static enum sys_con malta_sys_con(void)
int dram_init(void)
{
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
gd->ram_size = CFG_SYS_SDRAM_SIZE;
return 0;
}

2
board/imgtec/xilfpga/xilfpga.c
View File

@@ -19,7 +19,7 @@ int dram_init(void)
{
/* MIG IP block is smart and doesn't need SW
* to do any init */
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */
gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */
return 0;
}

2
board/inversepath/usbarmory/usbarmory.c
View File

@@ -412,7 +412,7 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 1 << 30);
return 0;
}

2
board/isee/igep003x/board.c
View File

@@ -185,7 +185,7 @@ int spl_start_uboot(void)
*/
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
gpmc_init();

4
board/keymile/common/common.c
View File

@@ -52,7 +52,7 @@ int set_km_env(void)
char envval[16];
char *p;
pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM;
sprintf(envval, "0x%x", pnvramaddr);
env_set("pnvramaddr", envval);
@@ -65,7 +65,7 @@ int set_km_env(void)
CONFIG_KM_PNVRAM) / 0x400;
env_set_ulong("pram", pram);
varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size -
varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size -
CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
env_set_hex("varaddr", varaddr);
sprintf(envval, "0x%x", varaddr);

6
board/keymile/km83xx/km83xx.c
View File

@@ -142,10 +142,10 @@ static int fixed_sdram(void)
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
disable_addr_trans();
msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
enable_addr_trans();
msize /= (1024 * 1024);
if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) {
if (CFG_SYS_SDRAM_SIZE >> 20 != msize) {
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size >> 1, ddr_size_log2++)
@@ -169,7 +169,7 @@ int dram_init(void)
return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar,
CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
CFG_SYS_SDRAM_BASE & LAWBAR_BAR);
msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)

2
board/keymile/pg-wcom-ls102xa/ddr.c
View File

@@ -84,7 +84,7 @@ int fsl_initdram(void)
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
return 0;

2
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
View File

@@ -184,7 +184,7 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
/* Define only 1MiB range for mem_regions at the middle of the RAM */
/* For 1GiB range mem_regions takes approx. 4min */
*vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
*vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1);
*size = 1 << 20;
return 0;
}

6
board/l+g/vinco/vinco.c
View File

@@ -164,7 +164,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
#if !CONFIG_IS_ENABLED(DM_SPI)
vinco_spi0_hw_init();
@@ -188,8 +188,8 @@ int board_init(void)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CFG_SYS_SDRAM_SIZE);
return 0;
}

2
board/mediatek/mt7622/mt7622_rfb.c
View File

@@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/mediatek/mt7623/mt7623_rfb.c
View File

@@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/mediatek/mt7629/mt7629_rfb.c
View File

@@ -11,7 +11,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/mediatek/mt8518/mt8518_ap1.c
View File

@@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
debug("gd->fdt_blob is %p\n", gd->fdt_blob);
return 0;

2
board/mscc/jr2/jr2.c
View File

@@ -28,7 +28,7 @@ int board_early_init_r(void)
ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}

2
board/mscc/luton/luton.c
View File

@@ -29,7 +29,7 @@ int board_early_init_r(void)
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}

2
board/mscc/ocelot/ocelot.c
View File

@@ -77,7 +77,7 @@ int board_early_init_r(void)
ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}

2
board/mscc/serval/serval.c
View File

@@ -22,7 +22,7 @@ int board_early_init_r(void)
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}

2
board/mscc/servalt/servalt.c
View File

@@ -22,7 +22,7 @@ int board_early_init_r(void)
writel(0, BASE_CFG + ICPU_SW_MODE);
/* Address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
return 0;
}

4
board/phytec/phycore_am335x_r2/board.c
View File

@@ -166,7 +166,7 @@ void sdram_init(void)
0);
/* Detect memory physically present */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
/* Reconfigure memory for actual detected size */
@@ -269,7 +269,7 @@ void set_mux_conf_regs(void)
*/
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/phytium/pomelo/pomelo.c
View File

@@ -24,7 +24,7 @@ int dram_init(void)
ddr_init();
gd->mem_clk = 0;
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000);
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000);
sec_init();
debug("PBF relocate done\n");

2
board/renesas/alt/alt.c
View File

@@ -70,7 +70,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");

2
board/renesas/blanche/blanche.c
View File

@@ -312,7 +312,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
return 0;
}

2
board/renesas/gose/gose.c
View File

@@ -78,7 +78,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");

2
board/renesas/grpeach/grpeach.c
View File

@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100);
return 0;
}

2
board/renesas/koelsch/koelsch.c
View File

@@ -80,7 +80,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");

2
board/renesas/lager/lager.c
View File

@@ -89,7 +89,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");

2
board/renesas/porter/porter.c
View File

@@ -78,7 +78,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");

2
board/renesas/silk/silk.c
View File

@@ -71,7 +71,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* Force ethernet PHY out of reset */
gpio_request(ETHERNET_PHY_RESET, "phy_reset");

2
board/renesas/stout/stout.c
View File

@@ -88,7 +88,7 @@ int board_early_init_f(void)
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
cpld_init();

Some files were not shown because too many files have changed in this diff Show More