From ddcccb2b2c1251ee9cd658c340d722a716d75a96 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 27 Feb 2020 16:00:51 +0200 Subject: [PATCH 1/5] x86: acpi: Refactor XSDT handling in acpi_add_table() There is no need to have an assignment to NULL for XSDT pointer. Therefore, no need to assign it when rsdt_address is not set. Because of above changes we may decrease indentation level as well. While here, drop unnecessary parentheses. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- arch/x86/lib/acpi_table.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 0d69cf271f4..66e32f21bdb 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -109,14 +109,11 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) { int i, entries_num; struct acpi_rsdt *rsdt; - struct acpi_xsdt *xsdt = NULL; + struct acpi_xsdt *xsdt; /* The RSDT is mandatory while the XSDT is not */ rsdt = (struct acpi_rsdt *)rsdp->rsdt_address; - if (rsdp->xsdt_address) - xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address); - /* This should always be MAX_ACPI_TABLES */ entries_num = ARRAY_SIZE(rsdt->entry); @@ -135,30 +132,34 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) /* Fix RSDT length or the kernel will assume invalid entries */ rsdt->header.length = sizeof(struct acpi_table_header) + - (sizeof(u32) * (i + 1)); + sizeof(u32) * (i + 1); /* Re-calculate checksum */ rsdt->header.checksum = 0; rsdt->header.checksum = table_compute_checksum((u8 *)rsdt, rsdt->header.length); + /* The RSDT is mandatory while the XSDT is not */ + if (!rsdp->xsdt_address) + return; + /* * And now the same thing for the XSDT. We use the same index as for * now we want the XSDT and RSDT to always be in sync in U-Boot */ - if (xsdt) { - /* Add table to the XSDT */ - xsdt->entry[i] = (u64)(u32)table; + xsdt = (struct acpi_xsdt *)((u32)rsdp->xsdt_address); - /* Fix XSDT length */ - xsdt->header.length = sizeof(struct acpi_table_header) + - (sizeof(u64) * (i + 1)); + /* Add table to the XSDT */ + xsdt->entry[i] = (u64)(u32)table; - /* Re-calculate checksum */ - xsdt->header.checksum = 0; - xsdt->header.checksum = table_compute_checksum((u8 *)xsdt, - xsdt->header.length); - } + /* Fix XSDT length */ + xsdt->header.length = sizeof(struct acpi_table_header) + + sizeof(u64) * (i + 1); + + /* Re-calculate checksum */ + xsdt->header.checksum = 0; + xsdt->header.checksum = table_compute_checksum((u8 *)xsdt, + xsdt->header.length); } static void acpi_create_facs(struct acpi_facs *facs) From 63a6098961a2e68ca03093bc45353f2bcc743981 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 5 Mar 2020 22:56:26 +0200 Subject: [PATCH 2/5] doc: board: verdin-imx8mm: use mainline TF-A 1. Update build steps where mainline Trusted Firmware A is used. 2. Fix BL31_BASE to the proper one according to the SoC reference manual. Signed-off-by: Igor Opaniuk Reviewed-by: Bin Meng --- doc/board/toradex/verdin-imx8mm.rst | 26 ++++++-------------------- 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/doc/board/toradex/verdin-imx8mm.rst b/doc/board/toradex/verdin-imx8mm.rst index b2ae4fabea9..b9f7dc39c96 100644 --- a/doc/board/toradex/verdin-imx8mm.rst +++ b/doc/board/toradex/verdin-imx8mm.rst @@ -18,31 +18,22 @@ Get and Build the ARM Trusted Firmware (Trusted Firmware A) .. code-block:: bash $ echo "Downloading and building TF-A..." - $ git clone -b imx_4.14.98_2.3.0 \ - https://source.codeaurora.org/external/imx/imx-atf - $ cd imx-atf - -Please edit ``plat/imx/imx8mm/include/platform_def.h`` so it contains proper -values for UART configuration and BL31 base address (correct values listed -below): - -.. code-block:: bash - - #define BL31_BASE 0x910000 - #define IMX_BOOT_UART_BASE 0x30860000 - #define DEBUG_CONSOLE 1 + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a Then build ATF (TF-A): .. code-block:: bash - $ make PLAT=imx8mm bl31 + $ make PLAT=imx8mm IMX_BOOT_UART_BASE=0x30860000 bl31 + $ cp build/imx8mm/release/bl31.bin ../ Get the DDR Firmware -------------------- .. code-block:: bash + $ cd .. $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.4.1.bin $ chmod +x firmware-imx-8.4.1.bin $ ./firmware-imx-8.4.1.bin @@ -53,6 +44,7 @@ Build U-Boot .. code-block:: bash $ export CROSS_COMPILE=aarch64-linux-gnu- + $ export ATF_LOAD_ADDR=0x920000 $ make verdin-imx8mm_defconfig $ make flash.bin @@ -89,12 +81,6 @@ Output: U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) Normal Boot Trying to boot from MMC1 - NOTICE: Configuring TZASC380 - NOTICE: RDC off - NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty - NOTICE: BL31: Built : 01:11:41, Jan 25 2020 - NOTICE: sip svc init - U-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100) From d0f7ab531057d666ebebeb8bb1860f52010e7a84 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 20 Mar 2020 19:59:21 +0200 Subject: [PATCH 3/5] =?UTF-8?q?x86:=20acpi:=20Add=20I=C2=B2C=20timings=20t?= =?UTF-8?q?o=20Intel=20Merrifield=20platform?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is established way to provide I²C timings, or actually counters, to the OS via ACPI. Fill them for Intel Merrifield platform. Signed-off-by: Andy Shevchenko Reviewed-by: Simon Glass --- .../asm/arch-tangier/acpi/southcluster.asl | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index c622783f44c..6ccdc25136e 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -240,6 +240,21 @@ Device (PCI0) Return (STA_VISIBLE) } + Name (SSCN, Package () + { + 0x02F8, 0x037B, Zero, + }) + + Name (FMCN, Package () + { + 0x0087, 0x010A, Zero, + }) + + Name (HSCN, Package () + { + 0x0008, 0x0020, Zero, + }) + Name (RBUF, ResourceTemplate() { FixedDMA(0x0009, 0x0000, Width32bit, ) @@ -260,6 +275,21 @@ Device (PCI0) { Return (STA_VISIBLE) } + + Name (SSCN, Package () + { + 0x02F8, 0x037B, Zero, + }) + + Name (FMCN, Package () + { + 0x0087, 0x010A, Zero, + }) + + Name (HSCN, Package () + { + 0x0008, 0x0020, Zero, + }) } Device (GPIO) From 4d073fa83bed62c65aeedb71c4b5584371dc59b7 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 26 Mar 2020 12:33:36 +0200 Subject: [PATCH 4/5] x86: acpi: Describe USB 3 host controller found on Intel Tangier USB 3 host controller may be described in ACPI to allow users alter the properties or other features. Describe it for Intel Tangier SoC. Signed-off-by: Andy Shevchenko Reviewed-by: Bin Meng --- .../asm/arch-tangier/acpi/southcluster.asl | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index 6ccdc25136e..f088fe3cf51 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -321,6 +321,53 @@ Device (PCI0) } } + Device (DWC3) + { + Name (_ADR, 0x00110000) + Name (_DEP, Package () + { + ^IPC1.PMIC + }) + + Method (_STA, 0, NotSerialized) + { + Return (STA_VISIBLE) + } + + Device (RHUB) + { + Name (_ADR, Zero) + + /* GPLD: Generate Port Location Data (PLD) */ + Method (GPLD, 1, Serialized) { + Name (PCKG, Package () { + Buffer (0x14) {} + }) + + /* REV: Revision 0x02 for ACPI 5.0 */ + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x0002, REV) + + /* VISI: Port visibility to user per port */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + + /* VOFF: Vertical offset is not supplied */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x80, 0x10, VOFF) + Store (0xFFFF, VOFF) + + /* HOFF: Horizontal offset is not supplied */ + CreateField (DerefOf (Index (PCKG, Zero)), 0x90, 0x10, HOFF) + Store (0xFFFF, HOFF) + + Return (PCKG) + } + + Device (HS01) { Name (_ADR, 1) } + Device (SS01) { Name (_ADR, 2) } + } + } + Device (PWM0) { Name (_ADR, 0x00170000) From 9e6ce62190b7cd874d2bf727c7681292551ba6b9 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 3 Apr 2020 18:35:32 -0700 Subject: [PATCH 5/5] serial: ns16550: Fix ordering of getting base address Currently the driver gets ns16550 base address in the driver probe() routine, which may potentially break any ns16550 wrapper driver that does additional initialization before calling ns16550_serial_probe(). Things are complicated that we need consider ns16550 devices on both simple-bus and PCI bus. To fix the issue we move the base address assignment for simple-bus ns16550 device back to the ofdata_to_platdata(), and assign base address for PCI ns16550 device in ns16550_serial_probe(). This is still not perfect. If any PCI bus based ns16550 wrapper driver tries to access plat->base before calling probe(), it is still subject to break. Fixes: 720f9e1fdb0c9 ("serial: ns16550: Move PCI access from ofdata_to_platdata() to probe()") Reported-by: Andy Shevchenko Signed-off-by: Bin Meng Tested-by: Andy Shevchenko Reviewed-by: Wolfgang Wallner Tested-by: Wolfgang Wallner --- drivers/serial/ns16550.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index c1b303ffcba..a2f1b356295 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -479,39 +479,38 @@ static int ns16550_serial_getinfo(struct udevice *dev, return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) -static int ns1655_serial_set_base_addr(struct udevice *dev) +static int ns16550_serial_assign_base(struct ns16550_platdata *plat, ulong base) { - fdt_addr_t addr; - struct ns16550_platdata *plat; - - plat = dev_get_platdata(dev); - - addr = dev_read_addr_pci(dev); - if (addr == FDT_ADDR_T_NONE) + if (base == FDT_ADDR_T_NONE) return -EINVAL; #ifdef CONFIG_SYS_NS16550_PORT_MAPPED - plat->base = addr; + plat->base = base; #else - plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); + plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE); #endif return 0; } -#endif int ns16550_serial_probe(struct udevice *dev) { + struct ns16550_platdata *plat = dev->platdata; struct NS16550 *const com_port = dev_get_priv(dev); struct reset_ctl_bulk reset_bulk; + fdt_addr_t addr; int ret; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) - ret = ns1655_serial_set_base_addr(dev); - if (ret) - return ret; -#endif + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, assign platdata->base before probing hardware. + */ + if (device_is_on_pci_bus(dev)) { + addr = devfdt_get_addr_pci(dev); + ret = ns16550_serial_assign_base(plat, addr); + if (ret) + return ret; + } ret = reset_get_bulk(dev, &reset_bulk); if (!ret) @@ -535,9 +534,15 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev->platdata; const u32 port_type = dev_get_driver_data(dev); + fdt_addr_t addr; struct clk clk; int err; + addr = dev_read_addr(dev); + err = ns16550_serial_assign_base(plat, addr); + if (err && !device_is_on_pci_bus(dev)) + return err; + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);