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[PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)

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This fix will make the MAL burst disabling patch for the Linux
EMAC driver obsolete.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2007-01-05 10:40:36 +01:00
parent 0238898382
commit a78bc443ae
2 changed files with 23 additions and 12 deletions
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15
board/amcc/sequoia/sequoia.c
View File

@@ -35,9 +35,9 @@ ulong flash_get_size (ulong base, int banknum);
int board_early_init_f(void)
{
unsigned long sdr0_cust0;
unsigned long sdr0_pfc1, sdr0_pfc2;
register uint reg;
u32 sdr0_cust0;
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
@@ -142,6 +142,7 @@ int misc_init_r(void)
{
uint pbcr;
int size_val = 0;
u32 reg;
#ifdef CONFIG_440EPX
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
@@ -335,6 +336,14 @@ int misc_init_r(void)
}
#endif /* CONFIG_440EPX */
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
mtdcr(plb4_acr, reg);
return 0;
}

20
include/ppc440.h
View File

@@ -887,12 +887,14 @@
/* PLB4 Arbiter - PowerPC440EP Pass1 */
#define PLB4_DCR_BASE 0x080
#define plb4_acr (PLB4_DCR_BASE+0x1)
#define plb4_revid (PLB4_DCR_BASE+0x2)
#define plb4_acr (PLB4_DCR_BASE+0x3)
#define plb4_besr (PLB4_DCR_BASE+0x4)
#define plb4_bearl (PLB4_DCR_BASE+0x6)
#define plb4_bearh (PLB4_DCR_BASE+0x7)
#define PLB4_ACR_WRP (0x80000000 >> 7)
/* Nebula PLB4 Arbiter - PowerPC440EP */
#define PLB_ARBITER_BASE 0x80
@@ -3284,26 +3286,26 @@ typedef struct { unsigned long add; /* gpio core base address */
/*
* Macros for accessing the indirect EBC registers
*/
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
#define mtebc(reg, data) { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); }
#define mfebc(reg, data) { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); }
/*
* Macros for accessing the indirect SDRAM controller registers
*/
#define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
#define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); }
#define mfsdram(reg, data) { mtdcr(memcfga,reg);data = mfdcr(memcfgd); }
/*
* Macros for accessing the indirect clocking controller registers
*/
#define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
#define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
#define mtclk(reg, data) { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); }
#define mfclk(reg, data) { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); }
/*
* Macros for accessing the sdr controller registers
*/
#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
#define mtsdr(reg, data) { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); }
#define mfsdr(reg, data) { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); }
#ifndef __ASSEMBLY__