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net: zynq_gem: Use clock driver for ZynqMP

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Enable and use the clock driver routine
defined in clock driver toset required
clock appropriately.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Siva Durga Prasad Paladugu
2016-11-15 16:15:42 +05:30
committed by Michal Simek
parent 128ec1fe6f
commit a765bdd1cb
2 changed files with 20 additions and 0 deletions
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2
arch/arm/include/asm/arch-zynqmp/sys_proto.h
View File

@@ -8,10 +8,12 @@
#ifndef _ASM_ARCH_SYS_PROTO_H #ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H
#ifndef CONFIG_CLK_ZYNQMP
/* Setup clk for network */ /* Setup clk for network */
static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{ {
} }
#endif
int zynq_slcr_get_mio_pin_status(const char *periph); int zynq_slcr_get_mio_pin_status(const char *periph);

18
drivers/net/zynq_gem.c
View File

@@ -9,6 +9,7 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#include <clk.h>
#include <common.h> #include <common.h>
#include <dm.h> #include <dm.h>
#include <net.h> #include <net.h>
@@ -181,6 +182,9 @@ struct zynq_gem_priv {
struct phy_device *phydev; struct phy_device *phydev;
int phy_of_handle; int phy_of_handle;
struct mii_dev *bus; struct mii_dev *bus;
#ifdef CONFIG_CLK_ZYNQMP
struct clk clk;
#endif
}; };
static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@@ -455,8 +459,14 @@ static int zynq_gem_init(struct udevice *dev)
/* Change the rclk and clk only not using EMIO interface */ /* Change the rclk and clk only not using EMIO interface */
if (!priv->emio) if (!priv->emio)
#ifndef CONFIG_CLK_ZYNQMP
zynq_slcr_gem_clk_setup((ulong)priv->iobase != zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
ZYNQ_GEM_BASEADDR0, clk_rate); ZYNQ_GEM_BASEADDR0, clk_rate);
#else
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret))
return -1;
#endif
setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK); ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -629,6 +639,14 @@ static int zynq_gem_probe(struct udevice *dev)
priv->tx_bd = (struct emac_bd *)bd_space; priv->tx_bd = (struct emac_bd *)bd_space;
priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
#ifdef CONFIG_CLK_ZYNQMP
ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
if (ret < 0) {
dev_err(dev, "failed to get clock\n");
return -EINVAL;
}
#endif
priv->bus = mdio_alloc(); priv->bus = mdio_alloc();
priv->bus->read = zynq_gem_miiphy_read; priv->bus->read = zynq_gem_miiphy_read;
priv->bus->write = zynq_gem_miiphy_write; priv->bus->write = zynq_gem_miiphy_write;