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powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving

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Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun
2012-08-17 08:22:39 +00:00
committed by Andy Fleming
parent fcea30688f
commit a4c66509f1
10 changed files with 488 additions and 319 deletions
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34
doc/README.fsl-ddr
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@@ -1,5 +1,28 @@
Table of interleaving 2-4 controllers
=====================================
+--------------+-----------------------------------------------------------+
|Configuration | Memory Controller |
| | 1 2 3 4 |
|--------------+--------------+--------------+-----------------------------+
| Two memory | Not Intlv'ed | Not Intlv'ed | |
| complexes +--------------+--------------+ |
| | 2-way Intlv'ed | |
|--------------+--------------+--------------+--------------+ |
| | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
| Three memory +--------------+--------------+--------------+ |
| complexes | 2-way Intlv'ed | Not Intlv'ed | |
| +-----------------------------+--------------+ |
| | 3-way Intlv'ed | |
+--------------+--------------+--------------+--------------+--------------+
| | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
| Four memory +--------------+--------------+--------------+--------------+
| complexes | 2-way Intlv'ed | 2-way Intlv'ed |
| +-----------------------------+-----------------------------+
| | 4-way Intlv'ed |
+--------------+-----------------------------------------------------------+
Table of interleaving modes supported in cpu/8xxx/ddr/
Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
======================================================
+-------------+---------------------------------------------------------+
| | Rank Interleaving |
@@ -56,6 +79,15 @@ The ways to configure the ddr interleaving mode
# superbank
setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
# 1KB 3-way interleaving
setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
# 4KB 3-way interleaving
setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
# 8KB 3-way interleaving
setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
# disable bank (chip-select) interleaving
setenv hwconfig "fsl_ddr:bank_intlv=null"