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fsl/ddr: updated ddr errata-A008378 for arm and power SoCs

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DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shengzhou Liu
2015-11-20 15:52:04 +08:00
committed by York Sun
parent a07bdad749
commit a46b1852de
3 changed files with 39 additions and 3 deletions
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31
include/fsl_errata.h
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@@ -58,4 +58,35 @@ static inline bool has_erratum_a007186(void)
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
static inline bool has_erratum_a008378(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
#ifdef CONFIG_LS102XA
case SOC_VER_LS1020:
case SOC_VER_LS1021:
case SOC_VER_LS1022:
case SOC_VER_SLS1020:
return IS_SVR_REV(svr, 1, 0);
#endif
#ifdef CONFIG_PPC
case SVR_T1023:
case SVR_T1024:
return IS_SVR_REV(svr, 1, 0);
case SVR_T1020:
case SVR_T1022:
case SVR_T1040:
case SVR_T1042:
return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
default:
return false;
}
}
#endif
#endif /* _FSL_ERRATA_H */