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arm: dts: mt7622: add USB nodes

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Add DTS nodes for MT7622/BPI-R64

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
This commit is contained in:
Frank Wunderlich
2020-08-20 16:37:57 +02:00
committed by Tom Rini
parent 28e1b1df3b
commit a13666b205
3 changed files with 72 additions and 0 deletions
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8
arch/arm/dts/mt7622-bananapi-bpi-r64.dts
View File

@@ -244,3 +244,11 @@
output-low; output-low;
}; };
}; };
&ssusb {
status = "okay";
};
&u3phy {
status = "okay";
};

8
arch/arm/dts/mt7622-rfb.dts
View File

@@ -222,3 +222,11 @@
full-duplex; full-duplex;
}; };
}; };
&ssusb {
status = "okay";
};
&u3phy {
status = "okay";
};

56
arch/arm/dts/mt7622.dtsi
View File

@@ -192,6 +192,14 @@
status = "disabled"; status = "disabled";
}; };
ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys",
"syscon";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pciesys: pciesys@1a100800 { pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon"; compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>; reg = <0x1a100800 0x1000>;
@@ -302,6 +310,54 @@
}; };
}; };
ssusb: usb@1a0c0000 {
compatible = "mediatek,mt7622-xhci",
"mediatek,mtk-xhci";
reg = <0x1a0c0000 0x01000>,
<0x1a0c4700 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
<&ssusbsys CLK_SSUSB_REF_EN>,
<&ssusbsys CLK_SSUSB_MCU_EN>,
<&ssusbsys CLK_SSUSB_DMA_EN>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
status = "disabled";
};
u3phy: usb-phy@1a0c4000 {
compatible = "mediatek,mt7622-u3phy",
"mediatek,generic-tphy-v1";
reg = <0x1a0c4000 0x700>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
u2port0: usb-phy@1a0c4800 {
reg = <0x1a0c4800 0x0100>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
clock-names = "ref";
};
u3port0: usb-phy@1a0c4900 {
reg = <0x1a0c4900 0x0700>;
#phy-cells = <1>;
};
u2port1: usb-phy@1a0c5000 {
reg = <0x1a0c5000 0x0100>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
clock-names = "ref";
};
};
ethsys: syscon@1b000000 { ethsys: syscon@1b000000 {
compatible = "mediatek,mt7622-ethsys", "syscon"; compatible = "mediatek,mt7622-ethsys", "syscon";
reg = <0x1b000000 0x1000>; reg = <0x1b000000 0x1000>;