mirror of
https://xff.cz/git/u-boot/
synced 2025-10-08 11:45:18 +02:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
@@ -65,6 +65,40 @@
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#define MT41J128MJT125_PHY_FIFO_WE 0x100
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#define MT41J128MJT125_IOCTRL_VALUE 0x18B
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/* Micron MT41J256M8HX-15E */
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#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
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#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
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#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
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#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
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#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
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#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
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#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
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#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
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#define MT41J256M8HX15E_RATIO 0x40
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#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
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#define MT41J256M8HX15E_RD_DQS 0x3B
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#define MT41J256M8HX15E_WR_DQS 0x85
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#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
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#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
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#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
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/* Micron MT41J512M8RH-125 on EVM v1.5 */
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#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
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#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
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#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
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#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
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#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
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#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
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#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
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#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
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#define MT41J512M8RH125_RATIO 0x80
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#define MT41J512M8RH125_INVERT_CLKOUT 0x0
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#define MT41J512M8RH125_RD_DQS 0x3B
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#define MT41J512M8RH125_WR_DQS 0x3C
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#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
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#define MT41J512M8RH125_PHY_WR_DATA 0x74
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#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
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/**
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* Configure SDRAM
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*/
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@@ -25,7 +25,8 @@
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/* PAD Control Fields */
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#define SLEWCTRL (0x1 << 6)
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#define RXACTIVE (0x1 << 5)
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#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
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#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
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#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
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#define PULLUDEN (0x0 << 3) /* Pull up enabled */
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#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
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#define MODE(val) val /* used for Readability */
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@@ -29,6 +29,7 @@
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#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
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#define BOOT_DEVICE_SPI 11
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#define BOOT_DEVICE_UART 65
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#define BOOT_DEVICE_USBETH 68
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#define BOOT_DEVICE_CPGMAC 70
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#define BOOT_DEVICE_MMC2_2 0xFF
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#endif
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|
@@ -31,37 +31,37 @@
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static inline unsigned long get_cpu_clk_rate(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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return gd->cpu_clk_rate_hz;
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return gd->arch.cpu_clk_rate_hz;
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}
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static inline unsigned long get_main_clk_rate(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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return gd->main_clk_rate_hz;
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return gd->arch.main_clk_rate_hz;
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}
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static inline unsigned long get_mck_clk_rate(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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return gd->mck_rate_hz;
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return gd->arch.mck_rate_hz;
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}
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static inline unsigned long get_plla_clk_rate(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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return gd->plla_rate_hz;
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return gd->arch.plla_rate_hz;
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}
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static inline unsigned long get_pllb_clk_rate(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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return gd->pllb_rate_hz;
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return gd->arch.pllb_rate_hz;
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}
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static inline u32 get_pllb_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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return gd->at91_pllb_usb_init;
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return gd->arch.at91_pllb_usb_init;
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}
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static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
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@@ -67,7 +67,11 @@ struct davinci_gpio_bank {
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#define gpio_status() gpio_info()
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#define GPIO_NAME_SIZE 20
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#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
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#define MAX_NUM_GPIOS 128
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#else
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#define MAX_NUM_GPIOS 144
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#endif
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#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
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#define GPIO_BIT(gp) ((gp) & 0x1F)
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@@ -23,67 +23,27 @@
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#include <asm/types.h>
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/* Stabilization delays, in usec */
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#define PLL_STABILIZATION_DELAY (300)
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#define PLL_STABILIZATION_DELAY (300)
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#define IO_STABILIZATION_DELAY (1000)
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#define NVBL_PLLP_KHZ (216000)
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#define PLLX_ENABLED (1 << 30)
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#define CCLK_BURST_POLICY 0x20008888
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#define SUPER_CCLK_DIVIDER 0x80000000
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/* Calculate clock fractional divider value from ref and target frequencies */
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#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
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#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
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/* Calculate clock frequency value from reference and clock divider value */
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#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
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#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
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/* AVP/CPU ID */
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#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
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#define PG_UP_TAG_0 0x0
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#define PG_UP_TAG_0 0x0
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#define CORESIGHT_UNLOCK 0xC5ACCE55;
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/* AP20-Specific Base Addresses */
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/* AP20 Base physical address of SDRAM. */
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#define AP20_BASE_PA_SDRAM 0x00000000
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/* AP20 Base physical address of internal SRAM. */
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#define AP20_BASE_PA_SRAM 0x40000000
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/* AP20 Size of internal SRAM (256KB). */
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#define AP20_BASE_PA_SRAM_SIZE 0x00040000
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/* AP20 Base physical address of flash. */
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#define AP20_BASE_PA_NOR_FLASH 0xD0000000
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/* AP20 Base physical address of boot information table. */
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#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
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/*
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* Super-temporary stacks for EXTREMELY early startup. The values chosen for
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* these addresses must be valid on ALL SOCs because this value is used before
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* we are able to differentiate between the SOC types.
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*
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* NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
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* stack is placed below the AVP stack. Once the CPU stack has been moved,
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* the AVP is free to use the IRAM the CPU stack previously occupied if
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* it should need to do so.
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*
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* NOTE: In multi-processor CPU complex configurations, each processor will have
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* its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
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* limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
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* stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
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* CPU.
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*/
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/* Common AVP early boot stack limit */
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#define AVP_EARLY_BOOT_STACK_LIMIT \
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(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
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/* Common AVP early boot stack size */
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#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
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/* Common CPU early boot stack limit */
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#define CPU_EARLY_BOOT_STACK_LIMIT \
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(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
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/* Common CPU early boot stack size */
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#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
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/* AP base physical address of internal SRAM */
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#define NV_PA_BASE_SRAM 0x40000000
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#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
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#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
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@@ -41,8 +41,9 @@ void gpio_early_init(void); /* overrideable GPIO config */
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* an empty stub function will be called.
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*/
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void pin_mux_usb(void); /* overrideable USB pinmux setup */
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void pin_mux_spi(void); /* overrideable SPI pinmux setup */
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void pin_mux_nand(void); /* overrideable NAND pinmux setup */
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void pin_mux_usb(void); /* overrideable USB pinmux setup */
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void pin_mux_spi(void); /* overrideable SPI pinmux setup */
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void pin_mux_nand(void); /* overrideable NAND pinmux setup */
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void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */
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#endif
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@@ -21,8 +21,8 @@
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* MA 02111-1307 USA
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*/
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#ifndef _CLK_RST_H_
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#define _CLK_RST_H_
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#ifndef _TEGRA_CLK_RST_H_
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#define _TEGRA_CLK_RST_H_
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/* PLL registers - there are several PLLs in the clock controller */
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struct clk_pll {
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@@ -37,6 +37,12 @@ struct clk_pll_simple {
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uint pll_misc; /* other misc things */
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};
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/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
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struct clk_set_clr {
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uint set;
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uint clr;
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};
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/*
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* Most PLLs use the clk_pll structure, but some have a simpler two-member
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* structure for which we use clk_pll_simple. The reason for this non-
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@@ -45,8 +51,10 @@ struct clk_pll_simple {
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enum {
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TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
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TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
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TEGRA_CLK_REGS = 3, /* Number of clock enable registers */
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TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */
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TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
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TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
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TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
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TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/
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};
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/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
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@@ -82,14 +90,80 @@ struct clk_rst_ctlr {
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uint crc_reserved11; /* _reserved_11, 0xFC */
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uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
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uint crc_reserved20[80]; /* 0x200-33C */
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uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
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uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
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uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */
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/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
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struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
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uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */
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/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
|
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struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
|
||||
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uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */
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uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
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uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
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||||
|
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/* Additional (T30) registers */
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||||
uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
|
||||
uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
|
||||
|
||||
uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */
|
||||
|
||||
uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
|
||||
uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
|
||||
uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
|
||||
uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
|
||||
uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
|
||||
uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
|
||||
uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
|
||||
uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
|
||||
uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
|
||||
uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTR1L_0, 0x384 */
|
||||
uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
|
||||
uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */
|
||||
uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
|
||||
/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
|
||||
struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
|
||||
/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
|
||||
struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
|
||||
/* Additional (T114) registers */
|
||||
uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
|
||||
uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
|
||||
uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
|
||||
uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
|
||||
uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
|
||||
uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
|
||||
uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
|
||||
uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
|
||||
uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
|
||||
uint crc_reserved40[1]; /* _reserved_40, 0x474 */
|
||||
uint crc_intstatus; /* __INTSTATUS_0, 0x478 */
|
||||
uint crc_intmask; /* __INTMASK_0, 0x47C */
|
||||
uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
|
||||
uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
|
||||
uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
|
||||
|
||||
uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */
|
||||
uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
|
||||
uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
|
||||
uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
|
||||
|
||||
uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
|
||||
uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
|
||||
uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
|
||||
uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
|
||||
uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
|
||||
uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
|
||||
uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
|
||||
};
|
||||
|
||||
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
|
||||
#define CPU3_CLK_STP_SHIFT 11
|
||||
#define CPU2_CLK_STP_SHIFT 10
|
||||
#define CPU1_CLK_STP_SHIFT 9
|
||||
|
||||
#define CPU0_CLK_STP_SHIFT 8
|
||||
#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
|
||||
|
||||
@@ -120,6 +194,12 @@ struct clk_rst_ctlr {
|
||||
#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
|
||||
|
||||
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
|
||||
#define PLL_DCCON_SHIFT 20
|
||||
#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
|
||||
|
||||
#define PLL_LOCK_ENABLE_SHIFT 18
|
||||
#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT)
|
||||
|
||||
#define PLL_CPCON_SHIFT 8
|
||||
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
|
||||
|
||||
@@ -129,9 +209,23 @@ struct clk_rst_ctlr {
|
||||
#define PLLU_VCO_FREQ_SHIFT 20
|
||||
#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
|
||||
|
||||
#define PLLP_OUT1_OVR (1 << 2)
|
||||
#define PLLP_OUT2_OVR (1 << 18)
|
||||
#define PLLP_OUT3_OVR (1 << 2)
|
||||
#define PLLP_OUT4_OVR (1 << 18)
|
||||
#define PLLP_OUT1_RATIO 8
|
||||
#define PLLP_OUT2_RATIO 24
|
||||
#define PLLP_OUT3_RATIO 8
|
||||
#define PLLP_OUT4_RATIO 24
|
||||
|
||||
enum {
|
||||
IN_408_OUT_204_DIVISOR = 2,
|
||||
IN_408_OUT_102_DIVISOR = 6,
|
||||
IN_408_OUT_48_DIVISOR = 15,
|
||||
IN_408_OUT_9_6_DIVISOR = 83,
|
||||
};
|
||||
|
||||
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
|
||||
#define OSC_FREQ_SHIFT 30
|
||||
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
|
||||
#define OSC_XOBP_SHIFT 1
|
||||
#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
|
||||
|
||||
@@ -151,4 +245,84 @@ struct clk_rst_ctlr {
|
||||
#define OUT_CLK_SOURCE4_SHIFT 28
|
||||
#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
|
||||
|
||||
#endif /* CLK_RST_H */
|
||||
/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
|
||||
#define SCLK_SYS_STATE_SHIFT 28U
|
||||
#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
|
||||
enum {
|
||||
SCLK_SYS_STATE_STDBY,
|
||||
SCLK_SYS_STATE_IDLE,
|
||||
SCLK_SYS_STATE_RUN,
|
||||
SCLK_SYS_STATE_IRQ = 4U,
|
||||
SCLK_SYS_STATE_FIQ = 8U,
|
||||
};
|
||||
#define SCLK_COP_FIQ_MASK (1 << 27)
|
||||
#define SCLK_CPU_FIQ_MASK (1 << 26)
|
||||
#define SCLK_COP_IRQ_MASK (1 << 25)
|
||||
#define SCLK_CPU_IRQ_MASK (1 << 24)
|
||||
|
||||
#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
|
||||
#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
|
||||
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
|
||||
#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
|
||||
#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
|
||||
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
|
||||
#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
|
||||
#define SCLK_SWAKEUP_RUN_SOURCE_MASK \
|
||||
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
|
||||
#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
|
||||
|
||||
#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
|
||||
(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
|
||||
enum {
|
||||
SCLK_SOURCE_CLKM,
|
||||
SCLK_SOURCE_PLLC_OUT1,
|
||||
SCLK_SOURCE_PLLP_OUT4,
|
||||
SCLK_SOURCE_PLLP_OUT3,
|
||||
SCLK_SOURCE_PLLP_OUT2,
|
||||
SCLK_SOURCE_CLKD,
|
||||
SCLK_SOURCE_CLKS,
|
||||
SCLK_SOURCE_PLLM_OUT1,
|
||||
};
|
||||
#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
|
||||
#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
|
||||
#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
|
||||
#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
|
||||
|
||||
/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
|
||||
#define SUPER_SCLK_ENB_SHIFT 31U
|
||||
#define SUPER_SCLK_ENB_MASK (1U << 31)
|
||||
#define SUPER_SCLK_DIVIDEND_SHIFT 8
|
||||
#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
|
||||
#define SUPER_SCLK_DIVISOR_SHIFT 0
|
||||
#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
|
||||
|
||||
/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
|
||||
#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
|
||||
#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
|
||||
#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
|
||||
#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
|
||||
#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
|
||||
#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
|
||||
#define CLK_SYS_RATE_APB_RATE_SHIFT 0
|
||||
#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
|
||||
|
||||
/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
|
||||
#define CLR_CPURESET0 (1 << 0)
|
||||
#define CLR_CPURESET1 (1 << 1)
|
||||
#define CLR_CPURESET2 (1 << 2)
|
||||
#define CLR_CPURESET3 (1 << 3)
|
||||
#define CLR_DBGRESET0 (1 << 12)
|
||||
#define CLR_DBGRESET1 (1 << 13)
|
||||
#define CLR_DBGRESET2 (1 << 14)
|
||||
#define CLR_DBGRESET3 (1 << 15)
|
||||
#define CLR_CORERESET0 (1 << 16)
|
||||
#define CLR_CORERESET1 (1 << 17)
|
||||
#define CLR_CORERESET2 (1 << 18)
|
||||
#define CLR_CORERESET3 (1 << 19)
|
||||
#define CLR_CXRESET0 (1 << 20)
|
||||
#define CLR_CXRESET1 (1 << 21)
|
||||
#define CLR_CXRESET2 (1 << 22)
|
||||
#define CLR_CXRESET3 (1 << 23)
|
||||
#define CLR_NONCPURESET (1 << 29)
|
||||
|
||||
#endif /* _TEGRA_CLK_RST_H_ */
|
||||
|
@@ -21,8 +21,8 @@
|
||||
|
||||
/* Tegra clock control functions */
|
||||
|
||||
#ifndef _CLOCK_H
|
||||
#define _CLOCK_H
|
||||
#ifndef _TEGRA_CLOCK_H_
|
||||
#define _TEGRA_CLOCK_H_
|
||||
|
||||
/* Set of oscillator frequencies supported in the internal API. */
|
||||
enum clock_osc_freq {
|
||||
@@ -82,7 +82,7 @@ int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
|
||||
* @returns 0 if ok, -1 on error (invalid clock id)
|
||||
*/
|
||||
int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
|
||||
u32 *divp, u32 *cpcon, u32 *lfcon);
|
||||
u32 *divp, u32 *cpcon, u32 *lfcon);
|
||||
|
||||
/*
|
||||
* Enable a clock
|
||||
@@ -136,7 +136,7 @@ enum crc_reset_id {
|
||||
/**
|
||||
* Put parts of the CPU complex into or out of reset.\
|
||||
*
|
||||
* @param cpu cpu number (0 or 1 on Tegra2)
|
||||
* @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
|
||||
* @param which which parts of the complex to affect (OR of crc_reset_id)
|
||||
* @param reset 1 to assert reset, 0 to de-assert
|
||||
*/
|
||||
@@ -262,4 +262,59 @@ void clock_init(void);
|
||||
/* Initialize the PLLs */
|
||||
void clock_early_init(void);
|
||||
|
||||
#endif /* _CLOCK_H_ */
|
||||
/* Returns a pointer to the clock source register for a peripheral */
|
||||
u32 *get_periph_source_reg(enum periph_id periph_id);
|
||||
|
||||
/**
|
||||
* Given a peripheral ID and the required source clock, this returns which
|
||||
* value should be programmed into the source mux for that peripheral.
|
||||
*
|
||||
* There is special code here to handle the one source type with 5 sources.
|
||||
*
|
||||
* @param periph_id peripheral to start
|
||||
* @param source PLL id of required parent clock
|
||||
* @param mux_bits Set to number of bits in mux register: 2 or 4
|
||||
* @param divider_bits Set to number of divider bits (8 or 16)
|
||||
* @return mux value (0-4, or -1 if not found)
|
||||
*/
|
||||
int get_periph_clock_source(enum periph_id periph_id,
|
||||
enum clock_id parent, int *mux_bits, int *divider_bits);
|
||||
|
||||
/*
|
||||
* Convert a device tree clock ID to our peripheral ID. They are mostly
|
||||
* the same but we are very cautious so we check that a valid clock ID is
|
||||
* provided.
|
||||
*
|
||||
* @param clk_id Clock ID according to tegra30 device tree binding
|
||||
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
|
||||
*/
|
||||
enum periph_id clk_id_to_periph_id(int clk_id);
|
||||
|
||||
/**
|
||||
* Set the output frequency you want for each PLL clock.
|
||||
* PLL output frequencies are programmed by setting their N, M and P values.
|
||||
* The governing equations are:
|
||||
* VCO = (Fi / m) * n, Fo = VCO / (2^p)
|
||||
* where Fo is the output frequency from the PLL.
|
||||
* Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
|
||||
* 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
|
||||
* Please see Tegra TRM section 5.3 to get the detail for PLL Programming
|
||||
*
|
||||
* @param n PLL feedback divider(DIVN)
|
||||
* @param m PLL input divider(DIVN)
|
||||
* @param p post divider(DIVP)
|
||||
* @param cpcon base PLL charge pump(CPCON)
|
||||
* @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
|
||||
* be overriden), 1 if PLL is already correct
|
||||
*/
|
||||
int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
|
||||
|
||||
/* return 1 if a peripheral ID is in range */
|
||||
#define clock_type_id_isvalid(id) ((id) >= 0 && \
|
||||
(id) < CLOCK_TYPE_COUNT)
|
||||
|
||||
/* return 1 if a periphc_internal_id is in range */
|
||||
#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
|
||||
(id) < PERIPHC_COUNT)
|
||||
|
||||
#endif /* _TEGRA_CLOCK_H_ */
|
||||
|
39
arch/arm/include/asm/arch-tegra/funcmux.h
Normal file
39
arch/arm/include/asm/arch-tegra/funcmux.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra high-level function multiplexing */
|
||||
|
||||
#ifndef _TEGRA_FUNCMUX_H_
|
||||
#define _TEGRA_FUNCMUX_H_
|
||||
|
||||
/**
|
||||
* Select a config for a particular peripheral.
|
||||
*
|
||||
* Each peripheral can operate through a number of configurations,
|
||||
* which are sets of pins that it uses to bring out its signals.
|
||||
* The basic config is 0, and higher numbers indicate different
|
||||
* pinmux settings to bring the peripheral out on other pins,
|
||||
*
|
||||
* This function also disables tristate for the function's pins,
|
||||
* so that they operate in normal mode.
|
||||
*
|
||||
* @param id Peripheral id
|
||||
* @param config Configuration to use (FUNCMUX_...), 0 for default
|
||||
* @return 0 if ok, -1 on error (e.g. incorrect id or config)
|
||||
*/
|
||||
int funcmux_select(enum periph_id id, int config);
|
||||
|
||||
#endif /* _TEGRA_FUNCMUX_H_ */
|
40
arch/arm/include/asm/arch-tegra/gp_padctrl.h
Normal file
40
arch/arm/include/asm/arch-tegra/gp_padctrl.h
Normal file
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* (C) Copyright 2010-2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA_GP_PADCTRL_H_
|
||||
#define _TEGRA_GP_PADCTRL_H_
|
||||
|
||||
#define GP_HIDREV 0x804
|
||||
|
||||
/* bit fields definitions for APB_MISC_GP_HIDREV register */
|
||||
#define HIDREV_CHIPID_SHIFT 8
|
||||
#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
|
||||
#define HIDREV_MAJORPREV_SHIFT 4
|
||||
#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
|
||||
|
||||
/* CHIPID field returned from APB_MISC_GP_HIDREV register */
|
||||
#define CHIPID_TEGRA20 0x20
|
||||
#define CHIPID_TEGRA30 0x30
|
||||
#define CHIPID_TEGRA114 0x35
|
||||
|
||||
#endif /* _TEGRA_GP_PADCTRL_H_ */
|
@@ -128,5 +128,13 @@ struct pmc_ctlr {
|
||||
#define START_CP (1 << 8)
|
||||
|
||||
#define CPUPWRREQ_OE (1 << 16)
|
||||
#define CPUPWRREQ_POL (1 << 15)
|
||||
|
||||
#define CRAILID (0)
|
||||
#define CE0ID (14)
|
||||
#define C0NCID (15)
|
||||
#define CRAIL (1 << CRAILID)
|
||||
#define CE0 (1 << CE0ID)
|
||||
#define C0NC (1 << C0NCID)
|
||||
|
||||
#endif /* PMC_H */
|
||||
|
@@ -40,6 +40,12 @@
|
||||
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
|
||||
#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
|
||||
#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
|
||||
#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
|
||||
#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
|
||||
#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
|
||||
#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
|
||||
#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
|
||||
#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
|
||||
#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
|
||||
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
|
||||
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
|
||||
@@ -72,14 +78,23 @@ enum {
|
||||
SKU_ID_T25 = 0x18,
|
||||
SKU_ID_AP25E = 0x1b,
|
||||
SKU_ID_T25E = 0x1c,
|
||||
SKU_ID_T30 = 0x81, /* Cardhu value */
|
||||
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
|
||||
};
|
||||
|
||||
/* These are the SOC categories that affect clocking */
|
||||
/*
|
||||
* These are used to distinguish SOC types for setting up clocks. Mostly
|
||||
* we can tell the clocking required by looking at the SOC sku_id, but
|
||||
* for T30 it is a user option as to whether to run PLLP in fast or slow
|
||||
* mode, so we have two options there.
|
||||
*/
|
||||
enum {
|
||||
TEGRA_SOC_T20,
|
||||
TEGRA_SOC_T25,
|
||||
TEGRA_SOC_T30,
|
||||
TEGRA_SOC_T114,
|
||||
|
||||
TEGRA_SOC_COUNT,
|
||||
TEGRA_SOC_CNT,
|
||||
TEGRA_SOC_UNKNOWN = -1,
|
||||
};
|
||||
|
||||
|
84
arch/arm/include/asm/arch-tegra/tegra_slink.h
Normal file
84
arch/arm/include/asm/arch-tegra/tegra_slink.h
Normal file
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* NVIDIA Tegra SPI-SLINK controller
|
||||
*
|
||||
* Copyright 2010-2013 NVIDIA Corporation
|
||||
*
|
||||
* This software may be used and distributed according to the
|
||||
* terms of the GNU Public License, Version 2, incorporated
|
||||
* herein by reference.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* Version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA_SLINK_H_
|
||||
#define _TEGRA_SLINK_H_
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
struct slink_tegra {
|
||||
u32 command; /* SLINK_COMMAND_0 register */
|
||||
u32 command2; /* SLINK_COMMAND2_0 reg */
|
||||
u32 status; /* SLINK_STATUS_0 register */
|
||||
u32 reserved; /* Reserved offset 0C */
|
||||
u32 mas_data; /* SLINK_MAS_DATA_0 reg */
|
||||
u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
|
||||
u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
|
||||
u32 status2; /* SLINK_STATUS2_0 reg */
|
||||
u32 rsvd[56]; /* 0x20 to 0xFF reserved */
|
||||
u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
|
||||
u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
|
||||
u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
|
||||
};
|
||||
|
||||
/* COMMAND */
|
||||
#define SLINK_CMD_ENB (1 << 31)
|
||||
#define SLINK_CMD_GO (1 << 30)
|
||||
#define SLINK_CMD_M_S (1 << 28)
|
||||
#define SLINK_CMD_CK_SDA (1 << 21)
|
||||
#define SLINK_CMD_CS_POL (1 << 13)
|
||||
#define SLINK_CMD_CS_VAL (1 << 12)
|
||||
#define SLINK_CMD_CS_SOFT (1 << 11)
|
||||
#define SLINK_CMD_BIT_LENGTH (1 << 4)
|
||||
#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F
|
||||
/* COMMAND2 */
|
||||
#define SLINK_CMD2_TXEN (1 << 30)
|
||||
#define SLINK_CMD2_RXEN (1 << 31)
|
||||
#define SLINK_CMD2_SS_EN (1 << 18)
|
||||
#define SLINK_CMD2_SS_EN_SHIFT 18
|
||||
#define SLINK_CMD2_SS_EN_MASK 0x000C0000
|
||||
#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17)
|
||||
/* STATUS */
|
||||
#define SLINK_STAT_BSY (1 << 31)
|
||||
#define SLINK_STAT_RDY (1 << 30)
|
||||
#define SLINK_STAT_ERR (1 << 29)
|
||||
#define SLINK_STAT_RXF_FLUSH (1 << 27)
|
||||
#define SLINK_STAT_TXF_FLUSH (1 << 26)
|
||||
#define SLINK_STAT_RXF_OVF (1 << 25)
|
||||
#define SLINK_STAT_TXF_UNR (1 << 24)
|
||||
#define SLINK_STAT_RXF_EMPTY (1 << 23)
|
||||
#define SLINK_STAT_RXF_FULL (1 << 22)
|
||||
#define SLINK_STAT_TXF_EMPTY (1 << 21)
|
||||
#define SLINK_STAT_TXF_FULL (1 << 20)
|
||||
#define SLINK_STAT_TXF_OVF (1 << 19)
|
||||
#define SLINK_STAT_RXF_UNR (1 << 18)
|
||||
#define SLINK_STAT_CUR_BLKCNT (1 << 15)
|
||||
/* STATUS2 */
|
||||
#define SLINK_STAT2_RXF_FULL_CNT (1 << 16)
|
||||
#define SLINK_STAT2_TXF_FULL_CNT (1 << 0)
|
||||
|
||||
#define SPI_TIMEOUT 1000
|
||||
#define TEGRA_SPI_MAX_FREQ 52000000
|
||||
|
||||
#endif /* _TEGRA_SLINK_H_ */
|
402
arch/arm/include/asm/arch-tegra114/clock-tables.h
Normal file
402
arch/arm/include/asm/arch-tegra114/clock-tables.h
Normal file
@@ -0,0 +1,402 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra114 clock PLL tables */
|
||||
|
||||
#ifndef _TEGRA114_CLOCK_TABLES_H_
|
||||
#define _TEGRA114_CLOCK_TABLES_H_
|
||||
|
||||
/* The PLLs supported by the hardware */
|
||||
enum clock_id {
|
||||
CLOCK_ID_FIRST,
|
||||
CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
|
||||
CLOCK_ID_MEMORY,
|
||||
CLOCK_ID_PERIPH,
|
||||
CLOCK_ID_AUDIO,
|
||||
CLOCK_ID_USB,
|
||||
CLOCK_ID_DISPLAY,
|
||||
|
||||
/* now the simple ones */
|
||||
CLOCK_ID_FIRST_SIMPLE,
|
||||
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
|
||||
CLOCK_ID_EPCI,
|
||||
CLOCK_ID_SFROM32KHZ,
|
||||
|
||||
/* These are the base clocks (inputs to the Tegra SOC) */
|
||||
CLOCK_ID_32KHZ,
|
||||
CLOCK_ID_OSC,
|
||||
|
||||
CLOCK_ID_COUNT, /* number of PLLs */
|
||||
CLOCK_ID_DISPLAY2, /* placeholder */
|
||||
CLOCK_ID_NONE = -1,
|
||||
};
|
||||
|
||||
/* The clocks supported by the hardware */
|
||||
enum periph_id {
|
||||
PERIPH_ID_FIRST,
|
||||
|
||||
/* Low word: 31:0 (DEVICES_L) */
|
||||
PERIPH_ID_CPU = PERIPH_ID_FIRST,
|
||||
PERIPH_ID_COP,
|
||||
PERIPH_ID_TRIGSYS,
|
||||
PERIPH_ID_RESERVED3,
|
||||
PERIPH_ID_RTC,
|
||||
PERIPH_ID_TMR,
|
||||
PERIPH_ID_UART1,
|
||||
PERIPH_ID_UART2,
|
||||
|
||||
/* 8 */
|
||||
PERIPH_ID_GPIO,
|
||||
PERIPH_ID_SDMMC2,
|
||||
PERIPH_ID_SPDIF,
|
||||
PERIPH_ID_I2S1,
|
||||
PERIPH_ID_I2C1,
|
||||
PERIPH_ID_NDFLASH,
|
||||
PERIPH_ID_SDMMC1,
|
||||
PERIPH_ID_SDMMC4,
|
||||
|
||||
/* 16 */
|
||||
PERIPH_ID_RESERVED16,
|
||||
PERIPH_ID_PWM,
|
||||
PERIPH_ID_I2S2,
|
||||
PERIPH_ID_EPP,
|
||||
PERIPH_ID_VI,
|
||||
PERIPH_ID_2D,
|
||||
PERIPH_ID_USBD,
|
||||
PERIPH_ID_ISP,
|
||||
|
||||
/* 24 */
|
||||
PERIPH_ID_3D,
|
||||
PERIPH_ID_RESERVED24,
|
||||
PERIPH_ID_DISP2,
|
||||
PERIPH_ID_DISP1,
|
||||
PERIPH_ID_HOST1X,
|
||||
PERIPH_ID_VCP,
|
||||
PERIPH_ID_I2S0,
|
||||
PERIPH_ID_CACHE2,
|
||||
|
||||
/* Middle word: 63:32 (DEVICES_H) */
|
||||
PERIPH_ID_MEM,
|
||||
PERIPH_ID_AHBDMA,
|
||||
PERIPH_ID_APBDMA,
|
||||
PERIPH_ID_RESERVED35,
|
||||
PERIPH_ID_KBC,
|
||||
PERIPH_ID_STAT_MON,
|
||||
PERIPH_ID_PMC,
|
||||
PERIPH_ID_FUSE,
|
||||
|
||||
/* 40 */
|
||||
PERIPH_ID_KFUSE,
|
||||
PERIPH_ID_SBC1,
|
||||
PERIPH_ID_SNOR,
|
||||
PERIPH_ID_RESERVED43,
|
||||
PERIPH_ID_SBC2,
|
||||
PERIPH_ID_RESERVED45,
|
||||
PERIPH_ID_SBC3,
|
||||
PERIPH_ID_I2C5,
|
||||
|
||||
/* 48 */
|
||||
PERIPH_ID_DSI,
|
||||
PERIPH_ID_TVO,
|
||||
PERIPH_ID_MIPI,
|
||||
PERIPH_ID_HDMI,
|
||||
PERIPH_ID_CSI,
|
||||
PERIPH_ID_TVDAC,
|
||||
PERIPH_ID_I2C2,
|
||||
PERIPH_ID_UART3,
|
||||
|
||||
/* 56 */
|
||||
PERIPH_ID_RESERVED56,
|
||||
PERIPH_ID_EMC,
|
||||
PERIPH_ID_USB2,
|
||||
PERIPH_ID_USB3,
|
||||
PERIPH_ID_MPE,
|
||||
PERIPH_ID_VDE,
|
||||
PERIPH_ID_BSEA,
|
||||
PERIPH_ID_BSEV,
|
||||
|
||||
/* Upper word 95:64 (DEVICES_U) */
|
||||
PERIPH_ID_SPEEDO,
|
||||
PERIPH_ID_UART4,
|
||||
PERIPH_ID_UART5,
|
||||
PERIPH_ID_I2C3,
|
||||
PERIPH_ID_SBC4,
|
||||
PERIPH_ID_SDMMC3,
|
||||
PERIPH_ID_PCIE,
|
||||
PERIPH_ID_OWR,
|
||||
|
||||
/* 72 */
|
||||
PERIPH_ID_AFI,
|
||||
PERIPH_ID_CORESIGHT,
|
||||
PERIPH_ID_PCIEXCLK,
|
||||
PERIPH_ID_AVPUCQ,
|
||||
PERIPH_ID_RESERVED76,
|
||||
PERIPH_ID_RESERVED77,
|
||||
PERIPH_ID_RESERVED78,
|
||||
PERIPH_ID_DTV,
|
||||
|
||||
/* 80 */
|
||||
PERIPH_ID_NANDSPEED,
|
||||
PERIPH_ID_I2CSLOW,
|
||||
PERIPH_ID_DSIB,
|
||||
PERIPH_ID_RESERVED83,
|
||||
PERIPH_ID_IRAMA,
|
||||
PERIPH_ID_IRAMB,
|
||||
PERIPH_ID_IRAMC,
|
||||
PERIPH_ID_IRAMD,
|
||||
|
||||
/* 88 */
|
||||
PERIPH_ID_CRAM2,
|
||||
PERIPH_ID_RESERVED89,
|
||||
PERIPH_ID_MDOUBLER,
|
||||
PERIPH_ID_RESERVED91,
|
||||
PERIPH_ID_SUSOUT,
|
||||
PERIPH_ID_RESERVED93,
|
||||
PERIPH_ID_RESERVED94,
|
||||
PERIPH_ID_RESERVED95,
|
||||
|
||||
PERIPH_ID_VW_FIRST,
|
||||
/* V word: 31:0 */
|
||||
PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
|
||||
PERIPH_ID_CPULP,
|
||||
PERIPH_ID_3D2,
|
||||
PERIPH_ID_MSELECT,
|
||||
PERIPH_ID_TSENSOR,
|
||||
PERIPH_ID_I2S3,
|
||||
PERIPH_ID_I2S4,
|
||||
PERIPH_ID_I2C4,
|
||||
|
||||
/* 104 */
|
||||
PERIPH_ID_SBC5,
|
||||
PERIPH_ID_SBC6,
|
||||
PERIPH_ID_AUDIO,
|
||||
PERIPH_ID_APBIF,
|
||||
PERIPH_ID_DAM0,
|
||||
PERIPH_ID_DAM1,
|
||||
PERIPH_ID_DAM2,
|
||||
PERIPH_ID_HDA2CODEC2X,
|
||||
|
||||
/* 112 */
|
||||
PERIPH_ID_ATOMICS,
|
||||
PERIPH_ID_EX_RESERVED17,
|
||||
PERIPH_ID_EX_RESERVED18,
|
||||
PERIPH_ID_EX_RESERVED19,
|
||||
PERIPH_ID_EX_RESERVED20,
|
||||
PERIPH_ID_EX_RESERVED21,
|
||||
PERIPH_ID_EX_RESERVED22,
|
||||
PERIPH_ID_ACTMON,
|
||||
|
||||
/* 120 */
|
||||
PERIPH_ID_EX_RESERVED24,
|
||||
PERIPH_ID_EX_RESERVED25,
|
||||
PERIPH_ID_EX_RESERVED26,
|
||||
PERIPH_ID_EX_RESERVED27,
|
||||
PERIPH_ID_SATA,
|
||||
PERIPH_ID_HDA,
|
||||
PERIPH_ID_EX_RESERVED30,
|
||||
PERIPH_ID_EX_RESERVED31,
|
||||
|
||||
/* W word: 31:0 */
|
||||
PERIPH_ID_HDA2HDMICODEC,
|
||||
PERIPH_ID_RESERVED1_SATACOLD,
|
||||
PERIPH_ID_RESERVED2_PCIERX0,
|
||||
PERIPH_ID_RESERVED3_PCIERX1,
|
||||
PERIPH_ID_RESERVED4_PCIERX2,
|
||||
PERIPH_ID_RESERVED5_PCIERX3,
|
||||
PERIPH_ID_RESERVED6_PCIERX4,
|
||||
PERIPH_ID_RESERVED7_PCIERX5,
|
||||
|
||||
/* 136 */
|
||||
PERIPH_ID_CEC,
|
||||
PERIPH_ID_PCIE2_IOBIST,
|
||||
PERIPH_ID_EMC_IOBIST,
|
||||
PERIPH_ID_HDMI_IOBIST,
|
||||
PERIPH_ID_SATA_IOBIST,
|
||||
PERIPH_ID_MIPI_IOBIST,
|
||||
PERIPH_ID_EMC1_IOBIST,
|
||||
PERIPH_ID_XUSB,
|
||||
|
||||
/* 144 */
|
||||
PERIPH_ID_CILAB,
|
||||
PERIPH_ID_CILCD,
|
||||
PERIPH_ID_CILE,
|
||||
PERIPH_ID_DSIA_LP,
|
||||
PERIPH_ID_DSIB_LP,
|
||||
PERIPH_ID_RESERVED21_ENTROPY,
|
||||
PERIPH_ID_RESERVED22_W,
|
||||
PERIPH_ID_RESERVED23_W,
|
||||
|
||||
/* 152 */
|
||||
PERIPH_ID_RESERVED24_W,
|
||||
PERIPH_ID_AMX0,
|
||||
PERIPH_ID_ADX0,
|
||||
PERIPH_ID_DVFS,
|
||||
PERIPH_ID_XUSB_SS,
|
||||
PERIPH_ID_EMC_DLL,
|
||||
PERIPH_ID_MC1,
|
||||
PERIPH_ID_EMC1,
|
||||
|
||||
PERIPH_ID_COUNT,
|
||||
PERIPH_ID_NONE = -1,
|
||||
};
|
||||
|
||||
enum pll_out_id {
|
||||
PLL_OUT1,
|
||||
PLL_OUT2,
|
||||
PLL_OUT3,
|
||||
PLL_OUT4
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
|
||||
* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
|
||||
* confusion bewteen PERIPH_ID_... and PERIPHC_...
|
||||
*
|
||||
* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
|
||||
* confusing.
|
||||
*/
|
||||
enum periphc_internal_id {
|
||||
/* 0x00 */
|
||||
PERIPHC_I2S1,
|
||||
PERIPHC_I2S2,
|
||||
PERIPHC_SPDIF_OUT,
|
||||
PERIPHC_SPDIF_IN,
|
||||
PERIPHC_PWM,
|
||||
PERIPHC_05h,
|
||||
PERIPHC_SBC2,
|
||||
PERIPHC_SBC3,
|
||||
|
||||
/* 0x08 */
|
||||
PERIPHC_08h,
|
||||
PERIPHC_I2C1,
|
||||
PERIPHC_I2C5,
|
||||
PERIPHC_0bh,
|
||||
PERIPHC_0ch,
|
||||
PERIPHC_SBC1,
|
||||
PERIPHC_DISP1,
|
||||
PERIPHC_DISP2,
|
||||
|
||||
/* 0x10 */
|
||||
PERIPHC_CVE,
|
||||
PERIPHC_11h,
|
||||
PERIPHC_VI,
|
||||
PERIPHC_13h,
|
||||
PERIPHC_SDMMC1,
|
||||
PERIPHC_SDMMC2,
|
||||
PERIPHC_G3D,
|
||||
PERIPHC_G2D,
|
||||
|
||||
/* 0x18 */
|
||||
PERIPHC_NDFLASH,
|
||||
PERIPHC_SDMMC4,
|
||||
PERIPHC_VFIR,
|
||||
PERIPHC_EPP,
|
||||
PERIPHC_MPE,
|
||||
PERIPHC_MIPI,
|
||||
PERIPHC_UART1,
|
||||
PERIPHC_UART2,
|
||||
|
||||
/* 0x20 */
|
||||
PERIPHC_HOST1X,
|
||||
PERIPHC_21h,
|
||||
PERIPHC_TVO,
|
||||
PERIPHC_HDMI,
|
||||
PERIPHC_24h,
|
||||
PERIPHC_TVDAC,
|
||||
PERIPHC_I2C2,
|
||||
PERIPHC_EMC,
|
||||
|
||||
/* 0x28 */
|
||||
PERIPHC_UART3,
|
||||
PERIPHC_29h,
|
||||
PERIPHC_VI_SENSOR,
|
||||
PERIPHC_2bh,
|
||||
PERIPHC_2ch,
|
||||
PERIPHC_SBC4,
|
||||
PERIPHC_I2C3,
|
||||
PERIPHC_SDMMC3,
|
||||
|
||||
/* 0x30 */
|
||||
PERIPHC_UART4,
|
||||
PERIPHC_UART5,
|
||||
PERIPHC_VDE,
|
||||
PERIPHC_OWR,
|
||||
PERIPHC_NOR,
|
||||
PERIPHC_CSITE,
|
||||
PERIPHC_I2S0,
|
||||
PERIPHC_37h,
|
||||
|
||||
PERIPHC_VW_FIRST,
|
||||
/* 0x38 */
|
||||
PERIPHC_G3D2 = PERIPHC_VW_FIRST,
|
||||
PERIPHC_MSELECT,
|
||||
PERIPHC_TSENSOR,
|
||||
PERIPHC_I2S3,
|
||||
PERIPHC_I2S4,
|
||||
PERIPHC_I2C4,
|
||||
PERIPHC_SBC5,
|
||||
PERIPHC_SBC6,
|
||||
|
||||
/* 0x40 */
|
||||
PERIPHC_AUDIO,
|
||||
PERIPHC_41h,
|
||||
PERIPHC_DAM0,
|
||||
PERIPHC_DAM1,
|
||||
PERIPHC_DAM2,
|
||||
PERIPHC_HDA2CODEC2X,
|
||||
PERIPHC_ACTMON,
|
||||
PERIPHC_EXTPERIPH1,
|
||||
|
||||
/* 0x48 */
|
||||
PERIPHC_EXTPERIPH2,
|
||||
PERIPHC_EXTPERIPH3,
|
||||
PERIPHC_NANDSPEED,
|
||||
PERIPHC_I2CSLOW,
|
||||
PERIPHC_SYS,
|
||||
PERIPHC_SPEEDO,
|
||||
PERIPHC_4eh,
|
||||
PERIPHC_4fh,
|
||||
|
||||
/* 0x50 */
|
||||
PERIPHC_50h,
|
||||
PERIPHC_51h,
|
||||
PERIPHC_52h,
|
||||
PERIPHC_53h,
|
||||
PERIPHC_SATAOOB,
|
||||
PERIPHC_SATA,
|
||||
PERIPHC_HDA,
|
||||
|
||||
PERIPHC_COUNT,
|
||||
|
||||
PERIPHC_NONE = -1,
|
||||
};
|
||||
|
||||
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
|
||||
#define PERIPH_REG(id) \
|
||||
(id < PERIPH_ID_VW_FIRST) ? \
|
||||
((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
|
||||
|
||||
/* Mask value for a clock (within PERIPH_REG(id)) */
|
||||
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
|
||||
|
||||
/* return 1 if a PLL ID is in range */
|
||||
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
|
||||
|
||||
/* return 1 if a peripheral ID is in range */
|
||||
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
|
||||
(id) < PERIPH_ID_COUNT)
|
||||
|
||||
#endif /* _TEGRA114_CLOCK_TABLES_H_ */
|
28
arch/arm/include/asm/arch-tegra114/clock.h
Normal file
28
arch/arm/include/asm/arch-tegra114/clock.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra114 clock control functions */
|
||||
|
||||
#ifndef _TEGRA114_CLOCK_H_
|
||||
#define _TEGRA114_CLOCK_H_
|
||||
|
||||
#include <asm/arch-tegra/clock.h>
|
||||
|
||||
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
|
||||
#define OSC_FREQ_SHIFT 28
|
||||
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
|
||||
|
||||
#endif /* _TEGRA114_CLOCK_H_ */
|
35
arch/arm/include/asm/arch-tegra114/flow.h
Normal file
35
arch/arm/include/asm/arch-tegra114/flow.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_FLOW_H_
|
||||
#define _TEGRA114_FLOW_H_
|
||||
|
||||
struct flow_ctlr {
|
||||
u32 halt_cpu_events;
|
||||
u32 halt_cop_events;
|
||||
u32 cpu_csr;
|
||||
u32 cop_csr;
|
||||
u32 xrq_events;
|
||||
u32 halt_cpu1_events;
|
||||
u32 cpu1_csr;
|
||||
u32 halt_cpu2_events;
|
||||
u32 cpu2_csr;
|
||||
u32 halt_cpu3_events;
|
||||
u32 cpu3_csr;
|
||||
u32 cluster_control;
|
||||
};
|
||||
|
||||
#endif /* _TEGRA114_FLOW_H_ */
|
31
arch/arm/include/asm/arch-tegra114/funcmux.h
Normal file
31
arch/arm/include/asm/arch-tegra114/funcmux.h
Normal file
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra114 high-level function multiplexing */
|
||||
|
||||
#ifndef _TEGRA114_FUNCMUX_H_
|
||||
#define _TEGRA114_FUNCMUX_H_
|
||||
|
||||
#include <asm/arch-tegra/funcmux.h>
|
||||
|
||||
/* Configs supported by the func mux */
|
||||
enum {
|
||||
FUNCMUX_DEFAULT = 0, /* default config */
|
||||
|
||||
/* UART configs */
|
||||
FUNCMUX_UART4_GMI = 0,
|
||||
};
|
||||
#endif /* _TEGRA114_FUNCMUX_H_ */
|
59
arch/arm/include/asm/arch-tegra114/gp_padctrl.h
Normal file
59
arch/arm/include/asm/arch-tegra114/gp_padctrl.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_GP_PADCTRL_H_
|
||||
#define _TEGRA114_GP_PADCTRL_H_
|
||||
|
||||
#include <asm/arch-tegra/gp_padctrl.h>
|
||||
|
||||
/* APB_MISC_GP and padctrl registers */
|
||||
struct apb_misc_gp_ctlr {
|
||||
u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
|
||||
u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
|
||||
u32 reserved0[22]; /* 0x08 - 0x5C: */
|
||||
u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
|
||||
u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
|
||||
u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
|
||||
u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
|
||||
u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
|
||||
u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
|
||||
u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
|
||||
u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
|
||||
u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
|
||||
u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
|
||||
u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
|
||||
u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
|
||||
u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
|
||||
u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
|
||||
u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
|
||||
u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
|
||||
u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
|
||||
u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
|
||||
u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
|
||||
u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
|
||||
u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
|
||||
u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
|
||||
u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
|
||||
u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
|
||||
u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
|
||||
u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
|
||||
u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
|
||||
u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
|
||||
u32 reserved1[7]; /* 0xD0-0xE8: */
|
||||
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
|
||||
};
|
||||
|
||||
#endif /* _TEGRA114_GP_PADCTRL_H_ */
|
30
arch/arm/include/asm/arch-tegra114/gpio.h
Normal file
30
arch/arm/include/asm/arch-tegra114/gpio.h
Normal file
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_GPIO_H_
|
||||
#define _TEGRA114_GPIO_H_
|
||||
|
||||
/*
|
||||
* The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports,
|
||||
* each with 8 GPIOs.
|
||||
*/
|
||||
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
|
||||
#define TEGRA_GPIO_BANKS 8 /* number of banks */
|
||||
|
||||
#include <asm/arch-tegra/gpio.h>
|
||||
#include <asm/arch-tegra30/gpio.h>
|
||||
|
||||
#endif /* _TEGRA114_GPIO_H_ */
|
22
arch/arm/include/asm/arch-tegra114/hardware.h
Normal file
22
arch/arm/include/asm/arch-tegra114/hardware.h
Normal file
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_HARDWARE_H_
|
||||
#define _TEGRA114_HARDWARE_H_
|
||||
|
||||
/* include tegra specific hardware definitions */
|
||||
|
||||
#endif /* _TEGRA114_HARDWARE_H_ */
|
618
arch/arm/include/asm/arch-tegra114/pinmux.h
Normal file
618
arch/arm/include/asm/arch-tegra114/pinmux.h
Normal file
@@ -0,0 +1,618 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_PINMUX_H_
|
||||
#define _TEGRA114_PINMUX_H_
|
||||
|
||||
/*
|
||||
* Pin groups which we adjust. There are three basic attributes of each pin
|
||||
* group which use this enum:
|
||||
*
|
||||
* - function
|
||||
* - pullup / pulldown
|
||||
* - tristate or normal
|
||||
*/
|
||||
enum pmux_pingrp {
|
||||
PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
|
||||
PINGRP_ULPI_DATA1,
|
||||
PINGRP_ULPI_DATA2,
|
||||
PINGRP_ULPI_DATA3,
|
||||
PINGRP_ULPI_DATA4,
|
||||
PINGRP_ULPI_DATA5,
|
||||
PINGRP_ULPI_DATA6,
|
||||
PINGRP_ULPI_DATA7,
|
||||
PINGRP_ULPI_CLK,
|
||||
PINGRP_ULPI_DIR,
|
||||
PINGRP_ULPI_NXT,
|
||||
PINGRP_ULPI_STP,
|
||||
PINGRP_DAP3_FS,
|
||||
PINGRP_DAP3_DIN,
|
||||
PINGRP_DAP3_DOUT,
|
||||
PINGRP_DAP3_SCLK,
|
||||
PINGRP_GPIO_PV0,
|
||||
PINGRP_GPIO_PV1,
|
||||
PINGRP_SDMMC1_CLK,
|
||||
PINGRP_SDMMC1_CMD,
|
||||
PINGRP_SDMMC1_DAT3,
|
||||
PINGRP_SDMMC1_DAT2,
|
||||
PINGRP_SDMMC1_DAT1,
|
||||
PINGRP_SDMMC1_DAT0,
|
||||
PINGRP_GPIO_PV2,
|
||||
PINGRP_GPIO_PV3,
|
||||
PINGRP_CLK2_OUT,
|
||||
PINGRP_CLK2_REQ,
|
||||
PINGRP_LCD_PWR1,
|
||||
PINGRP_LCD_PWR2,
|
||||
PINGRP_LCD_SDIN,
|
||||
PINGRP_LCD_SDOUT,
|
||||
PINGRP_LCD_WR_N,
|
||||
PINGRP_LCD_CS0_N,
|
||||
PINGRP_LCD_DC0,
|
||||
PINGRP_LCD_SCK,
|
||||
PINGRP_LCD_PWR0,
|
||||
PINGRP_LCD_PCLK,
|
||||
PINGRP_LCD_DE,
|
||||
PINGRP_LCD_HSYNC,
|
||||
PINGRP_LCD_VSYNC,
|
||||
PINGRP_LCD_D0,
|
||||
PINGRP_LCD_D1,
|
||||
PINGRP_LCD_D2,
|
||||
PINGRP_LCD_D3,
|
||||
PINGRP_LCD_D4,
|
||||
PINGRP_LCD_D5,
|
||||
PINGRP_LCD_D6,
|
||||
PINGRP_LCD_D7,
|
||||
PINGRP_LCD_D8,
|
||||
PINGRP_LCD_D9,
|
||||
PINGRP_LCD_D10,
|
||||
PINGRP_LCD_D11,
|
||||
PINGRP_LCD_D12,
|
||||
PINGRP_LCD_D13,
|
||||
PINGRP_LCD_D14,
|
||||
PINGRP_LCD_D15,
|
||||
PINGRP_LCD_D16,
|
||||
PINGRP_LCD_D17,
|
||||
PINGRP_LCD_D18,
|
||||
PINGRP_LCD_D19,
|
||||
PINGRP_LCD_D20,
|
||||
PINGRP_LCD_D21,
|
||||
PINGRP_LCD_D22,
|
||||
PINGRP_LCD_D23,
|
||||
PINGRP_LCD_CS1_N,
|
||||
PINGRP_LCD_M1,
|
||||
PINGRP_LCD_DC1,
|
||||
PINGRP_HDMI_INT,
|
||||
PINGRP_DDC_SCL,
|
||||
PINGRP_DDC_SDA,
|
||||
PINGRP_CRT_HSYNC,
|
||||
PINGRP_CRT_VSYNC,
|
||||
PINGRP_VI_D0,
|
||||
PINGRP_VI_D1,
|
||||
PINGRP_VI_D2,
|
||||
PINGRP_VI_D3,
|
||||
PINGRP_VI_D4,
|
||||
PINGRP_VI_D5,
|
||||
PINGRP_VI_D6,
|
||||
PINGRP_VI_D7,
|
||||
PINGRP_VI_D8,
|
||||
PINGRP_VI_D9,
|
||||
PINGRP_VI_D10,
|
||||
PINGRP_VI_D11,
|
||||
PINGRP_VI_PCLK,
|
||||
PINGRP_VI_MCLK,
|
||||
PINGRP_VI_VSYNC,
|
||||
PINGRP_VI_HSYNC,
|
||||
PINGRP_UART2_RXD,
|
||||
PINGRP_UART2_TXD,
|
||||
PINGRP_UART2_RTS_N,
|
||||
PINGRP_UART2_CTS_N,
|
||||
PINGRP_UART3_TXD,
|
||||
PINGRP_UART3_RXD,
|
||||
PINGRP_UART3_CTS_N,
|
||||
PINGRP_UART3_RTS_N,
|
||||
PINGRP_GPIO_PU0,
|
||||
PINGRP_GPIO_PU1,
|
||||
PINGRP_GPIO_PU2,
|
||||
PINGRP_GPIO_PU3,
|
||||
PINGRP_GPIO_PU4,
|
||||
PINGRP_GPIO_PU5,
|
||||
PINGRP_GPIO_PU6,
|
||||
PINGRP_GEN1_I2C_SDA,
|
||||
PINGRP_GEN1_I2C_SCL,
|
||||
PINGRP_DAP4_FS,
|
||||
PINGRP_DAP4_DIN,
|
||||
PINGRP_DAP4_DOUT,
|
||||
PINGRP_DAP4_SCLK,
|
||||
PINGRP_CLK3_OUT,
|
||||
PINGRP_CLK3_REQ,
|
||||
PINGRP_GMI_WP_N,
|
||||
PINGRP_GMI_IORDY,
|
||||
PINGRP_GMI_WAIT,
|
||||
PINGRP_GMI_ADV_N,
|
||||
PINGRP_GMI_CLK,
|
||||
PINGRP_GMI_CS0_N,
|
||||
PINGRP_GMI_CS1_N,
|
||||
PINGRP_GMI_CS2_N,
|
||||
PINGRP_GMI_CS3_N,
|
||||
PINGRP_GMI_CS4_N,
|
||||
PINGRP_GMI_CS6_N,
|
||||
PINGRP_GMI_CS7_N,
|
||||
PINGRP_GMI_AD0,
|
||||
PINGRP_GMI_AD1,
|
||||
PINGRP_GMI_AD2,
|
||||
PINGRP_GMI_AD3,
|
||||
PINGRP_GMI_AD4,
|
||||
PINGRP_GMI_AD5,
|
||||
PINGRP_GMI_AD6,
|
||||
PINGRP_GMI_AD7,
|
||||
PINGRP_GMI_AD8,
|
||||
PINGRP_GMI_AD9,
|
||||
PINGRP_GMI_AD10,
|
||||
PINGRP_GMI_AD11,
|
||||
PINGRP_GMI_AD12,
|
||||
PINGRP_GMI_AD13,
|
||||
PINGRP_GMI_AD14,
|
||||
PINGRP_GMI_AD15,
|
||||
PINGRP_GMI_A16,
|
||||
PINGRP_GMI_A17,
|
||||
PINGRP_GMI_A18,
|
||||
PINGRP_GMI_A19,
|
||||
PINGRP_GMI_WR_N,
|
||||
PINGRP_GMI_OE_N,
|
||||
PINGRP_GMI_DQS,
|
||||
PINGRP_GMI_RST_N,
|
||||
PINGRP_GEN2_I2C_SCL,
|
||||
PINGRP_GEN2_I2C_SDA,
|
||||
PINGRP_SDMMC4_CLK,
|
||||
PINGRP_SDMMC4_CMD,
|
||||
PINGRP_SDMMC4_DAT0,
|
||||
PINGRP_SDMMC4_DAT1,
|
||||
PINGRP_SDMMC4_DAT2,
|
||||
PINGRP_SDMMC4_DAT3,
|
||||
PINGRP_SDMMC4_DAT4,
|
||||
PINGRP_SDMMC4_DAT5,
|
||||
PINGRP_SDMMC4_DAT6,
|
||||
PINGRP_SDMMC4_DAT7,
|
||||
PINGRP_SDMMC4_RST_N,
|
||||
PINGRP_CAM_MCLK,
|
||||
PINGRP_GPIO_PCC1,
|
||||
PINGRP_GPIO_PBB0,
|
||||
PINGRP_CAM_I2C_SCL,
|
||||
PINGRP_CAM_I2C_SDA,
|
||||
PINGRP_GPIO_PBB3,
|
||||
PINGRP_GPIO_PBB4,
|
||||
PINGRP_GPIO_PBB5,
|
||||
PINGRP_GPIO_PBB6,
|
||||
PINGRP_GPIO_PBB7,
|
||||
PINGRP_GPIO_PCC2,
|
||||
PINGRP_JTAG_RTCK,
|
||||
PINGRP_PWR_I2C_SCL,
|
||||
PINGRP_PWR_I2C_SDA,
|
||||
PINGRP_KB_ROW0,
|
||||
PINGRP_KB_ROW1,
|
||||
PINGRP_KB_ROW2,
|
||||
PINGRP_KB_ROW3,
|
||||
PINGRP_KB_ROW4,
|
||||
PINGRP_KB_ROW5,
|
||||
PINGRP_KB_ROW6,
|
||||
PINGRP_KB_ROW7,
|
||||
PINGRP_KB_ROW8,
|
||||
PINGRP_KB_ROW9,
|
||||
PINGRP_KB_ROW10,
|
||||
PINGRP_KB_ROW11,
|
||||
PINGRP_KB_ROW12,
|
||||
PINGRP_KB_ROW13,
|
||||
PINGRP_KB_ROW14,
|
||||
PINGRP_KB_ROW15,
|
||||
PINGRP_KB_COL0,
|
||||
PINGRP_KB_COL1,
|
||||
PINGRP_KB_COL2,
|
||||
PINGRP_KB_COL3,
|
||||
PINGRP_KB_COL4,
|
||||
PINGRP_KB_COL5,
|
||||
PINGRP_KB_COL6,
|
||||
PINGRP_KB_COL7,
|
||||
PINGRP_CLK_32K_OUT,
|
||||
PINGRP_SYS_CLK_REQ,
|
||||
PINGRP_CORE_PWR_REQ,
|
||||
PINGRP_CPU_PWR_REQ,
|
||||
PINGRP_PWR_INT_N,
|
||||
PINGRP_CLK_32K_IN,
|
||||
PINGRP_OWR,
|
||||
PINGRP_DAP1_FS,
|
||||
PINGRP_DAP1_DIN,
|
||||
PINGRP_DAP1_DOUT,
|
||||
PINGRP_DAP1_SCLK,
|
||||
PINGRP_CLK1_REQ,
|
||||
PINGRP_CLK1_OUT,
|
||||
PINGRP_SPDIF_IN,
|
||||
PINGRP_SPDIF_OUT,
|
||||
PINGRP_DAP2_FS,
|
||||
PINGRP_DAP2_DIN,
|
||||
PINGRP_DAP2_DOUT,
|
||||
PINGRP_DAP2_SCLK,
|
||||
PINGRP_SPI2_MOSI,
|
||||
PINGRP_SPI2_MISO,
|
||||
PINGRP_SPI2_CS0_N,
|
||||
PINGRP_SPI2_SCK,
|
||||
PINGRP_SPI1_MOSI,
|
||||
PINGRP_SPI1_SCK,
|
||||
PINGRP_SPI1_CS0_N,
|
||||
PINGRP_SPI1_MISO,
|
||||
PINGRP_SPI2_CS1_N,
|
||||
PINGRP_SPI2_CS2_N,
|
||||
PINGRP_SDMMC3_CLK,
|
||||
PINGRP_SDMMC3_CMD,
|
||||
PINGRP_SDMMC3_DAT0,
|
||||
PINGRP_SDMMC3_DAT1,
|
||||
PINGRP_SDMMC3_DAT2,
|
||||
PINGRP_SDMMC3_DAT3,
|
||||
PINGRP_SDMMC3_DAT4,
|
||||
PINGRP_SDMMC3_DAT5,
|
||||
PINGRP_SDMMC3_DAT6,
|
||||
PINGRP_SDMMC3_DAT7,
|
||||
PINGRP_PEX_L0_PRSNT_N,
|
||||
PINGRP_PEX_L0_RST_N,
|
||||
PINGRP_PEX_L0_CLKREQ_N,
|
||||
PINGRP_PEX_WAKE_N,
|
||||
PINGRP_PEX_L1_PRSNT_N,
|
||||
PINGRP_PEX_L1_RST_N,
|
||||
PINGRP_PEX_L1_CLKREQ_N,
|
||||
PINGRP_PEX_L2_PRSNT_N,
|
||||
PINGRP_PEX_L2_RST_N,
|
||||
PINGRP_PEX_L2_CLKREQ_N,
|
||||
PINGRP_HDMI_CEC, /* offset 0x33e0 */
|
||||
PINGRP_SDMMC1_WP_N,
|
||||
PINGRP_SDMMC3_CD_N,
|
||||
PINGRP_SPI1_CS1_N,
|
||||
PINGRP_SPI1_CS2_N,
|
||||
PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
|
||||
PINGRP_USB_VBUS_EN1,
|
||||
PINGRP_SDMMC3_CLK_LB_IN,
|
||||
PINGRP_SDMMC3_CLK_LB_OUT,
|
||||
PINGRP_NAND_GMI_CLK_LB,
|
||||
PINGRP_RESET_OUT_N,
|
||||
PINGRP_COUNT,
|
||||
};
|
||||
|
||||
enum pdrive_pingrp {
|
||||
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
|
||||
PDRIVE_PINGROUP_AO2,
|
||||
PDRIVE_PINGROUP_AT1,
|
||||
PDRIVE_PINGROUP_AT2,
|
||||
PDRIVE_PINGROUP_AT3,
|
||||
PDRIVE_PINGROUP_AT4,
|
||||
PDRIVE_PINGROUP_AT5,
|
||||
PDRIVE_PINGROUP_CDEV1,
|
||||
PDRIVE_PINGROUP_CDEV2,
|
||||
PDRIVE_PINGROUP_CSUS,
|
||||
PDRIVE_PINGROUP_DAP1,
|
||||
PDRIVE_PINGROUP_DAP2,
|
||||
PDRIVE_PINGROUP_DAP3,
|
||||
PDRIVE_PINGROUP_DAP4,
|
||||
PDRIVE_PINGROUP_DBG,
|
||||
PDRIVE_PINGROUP_LCD1,
|
||||
PDRIVE_PINGROUP_LCD2,
|
||||
PDRIVE_PINGROUP_SDIO2,
|
||||
PDRIVE_PINGROUP_SDIO3,
|
||||
PDRIVE_PINGROUP_SPI,
|
||||
PDRIVE_PINGROUP_UAA,
|
||||
PDRIVE_PINGROUP_UAB,
|
||||
PDRIVE_PINGROUP_UART2,
|
||||
PDRIVE_PINGROUP_UART3,
|
||||
PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
|
||||
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
|
||||
PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
|
||||
PDRIVE_PINGROUP_DDC,
|
||||
PDRIVE_PINGROUP_GMA,
|
||||
PDRIVE_PINGROUP_GMB,
|
||||
PDRIVE_PINGROUP_GMC,
|
||||
PDRIVE_PINGROUP_GMD,
|
||||
PDRIVE_PINGROUP_GME,
|
||||
PDRIVE_PINGROUP_GMF,
|
||||
PDRIVE_PINGROUP_GMG,
|
||||
PDRIVE_PINGROUP_GMH,
|
||||
PDRIVE_PINGROUP_OWR,
|
||||
PDRIVE_PINGROUP_UAD,
|
||||
PDRIVE_PINGROUP_GPV,
|
||||
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
|
||||
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
|
||||
PDRIVE_PINGROUP_AT6,
|
||||
PDRIVE_PINGROUP_DAP5,
|
||||
PDRIVE_PINGROUP_VBUS,
|
||||
PDRIVE_PINGROUP_COUNT,
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions which can be assigned to each of the pin groups. The values here
|
||||
* bear no relation to the values programmed into pinmux registers and are
|
||||
* purely a convenience. The translation is done through a table search.
|
||||
*/
|
||||
enum pmux_func {
|
||||
PMUX_FUNC_AHB_CLK,
|
||||
PMUX_FUNC_APB_CLK,
|
||||
PMUX_FUNC_AUDIO_SYNC,
|
||||
PMUX_FUNC_CRT,
|
||||
PMUX_FUNC_DAP1,
|
||||
PMUX_FUNC_DAP2,
|
||||
PMUX_FUNC_DAP3,
|
||||
PMUX_FUNC_DAP4,
|
||||
PMUX_FUNC_DAP5,
|
||||
PMUX_FUNC_DISPA,
|
||||
PMUX_FUNC_DISPB,
|
||||
PMUX_FUNC_EMC_TEST0_DLL,
|
||||
PMUX_FUNC_EMC_TEST1_DLL,
|
||||
PMUX_FUNC_GMI,
|
||||
PMUX_FUNC_GMI_INT,
|
||||
PMUX_FUNC_HDMI,
|
||||
PMUX_FUNC_I2C1,
|
||||
PMUX_FUNC_I2C2,
|
||||
PMUX_FUNC_I2C3,
|
||||
PMUX_FUNC_IDE,
|
||||
PMUX_FUNC_KBC,
|
||||
PMUX_FUNC_MIO,
|
||||
PMUX_FUNC_MIPI_HS,
|
||||
PMUX_FUNC_NAND,
|
||||
PMUX_FUNC_OSC,
|
||||
PMUX_FUNC_OWR,
|
||||
PMUX_FUNC_PCIE,
|
||||
PMUX_FUNC_PLLA_OUT,
|
||||
PMUX_FUNC_PLLC_OUT1,
|
||||
PMUX_FUNC_PLLM_OUT1,
|
||||
PMUX_FUNC_PLLP_OUT2,
|
||||
PMUX_FUNC_PLLP_OUT3,
|
||||
PMUX_FUNC_PLLP_OUT4,
|
||||
PMUX_FUNC_PWM,
|
||||
PMUX_FUNC_PWR_INTR,
|
||||
PMUX_FUNC_PWR_ON,
|
||||
PMUX_FUNC_RTCK,
|
||||
PMUX_FUNC_SDMMC1,
|
||||
PMUX_FUNC_SDMMC2,
|
||||
PMUX_FUNC_SDMMC3,
|
||||
PMUX_FUNC_SDMMC4,
|
||||
PMUX_FUNC_SFLASH,
|
||||
PMUX_FUNC_SPDIF,
|
||||
PMUX_FUNC_SPI1,
|
||||
PMUX_FUNC_SPI2,
|
||||
PMUX_FUNC_SPI2_ALT,
|
||||
PMUX_FUNC_SPI3,
|
||||
PMUX_FUNC_SPI4,
|
||||
PMUX_FUNC_TRACE,
|
||||
PMUX_FUNC_TWC,
|
||||
PMUX_FUNC_UARTA,
|
||||
PMUX_FUNC_UARTB,
|
||||
PMUX_FUNC_UARTC,
|
||||
PMUX_FUNC_UARTD,
|
||||
PMUX_FUNC_UARTE,
|
||||
PMUX_FUNC_ULPI,
|
||||
PMUX_FUNC_VI,
|
||||
PMUX_FUNC_VI_SENSOR_CLK,
|
||||
PMUX_FUNC_XIO,
|
||||
PMUX_FUNC_BLINK,
|
||||
PMUX_FUNC_CEC,
|
||||
PMUX_FUNC_CLK12,
|
||||
PMUX_FUNC_DAP,
|
||||
PMUX_FUNC_DAPSDMMC2,
|
||||
PMUX_FUNC_DDR,
|
||||
PMUX_FUNC_DEV3,
|
||||
PMUX_FUNC_DTV,
|
||||
PMUX_FUNC_VI_ALT1,
|
||||
PMUX_FUNC_VI_ALT2,
|
||||
PMUX_FUNC_VI_ALT3,
|
||||
PMUX_FUNC_EMC_DLL,
|
||||
PMUX_FUNC_EXTPERIPH1,
|
||||
PMUX_FUNC_EXTPERIPH2,
|
||||
PMUX_FUNC_EXTPERIPH3,
|
||||
PMUX_FUNC_GMI_ALT,
|
||||
PMUX_FUNC_HDA,
|
||||
PMUX_FUNC_HSI,
|
||||
PMUX_FUNC_I2C4,
|
||||
PMUX_FUNC_I2C5,
|
||||
PMUX_FUNC_I2CPWR,
|
||||
PMUX_FUNC_I2S0,
|
||||
PMUX_FUNC_I2S1,
|
||||
PMUX_FUNC_I2S2,
|
||||
PMUX_FUNC_I2S3,
|
||||
PMUX_FUNC_I2S4,
|
||||
PMUX_FUNC_NAND_ALT,
|
||||
PMUX_FUNC_POPSDIO4,
|
||||
PMUX_FUNC_POPSDMMC4,
|
||||
PMUX_FUNC_PWM0,
|
||||
PMUX_FUNC_PWM1,
|
||||
PMUX_FUNC_PWM2,
|
||||
PMUX_FUNC_PWM3,
|
||||
PMUX_FUNC_SATA,
|
||||
PMUX_FUNC_SPI5,
|
||||
PMUX_FUNC_SPI6,
|
||||
PMUX_FUNC_SYSCLK,
|
||||
PMUX_FUNC_VGP1,
|
||||
PMUX_FUNC_VGP2,
|
||||
PMUX_FUNC_VGP3,
|
||||
PMUX_FUNC_VGP4,
|
||||
PMUX_FUNC_VGP5,
|
||||
PMUX_FUNC_VGP6,
|
||||
|
||||
PMUX_FUNC_USB,
|
||||
PMUX_FUNC_SOC,
|
||||
PMUX_FUNC_CPU,
|
||||
PMUX_FUNC_CLK,
|
||||
PMUX_FUNC_PWRON,
|
||||
PMUX_FUNC_PMI,
|
||||
PMUX_FUNC_CLDVFS,
|
||||
PMUX_FUNC_RESET_OUT_N,
|
||||
|
||||
PMUX_FUNC_SAFE,
|
||||
PMUX_FUNC_MAX,
|
||||
|
||||
PMUX_FUNC_RSVD1 = 0x8000,
|
||||
PMUX_FUNC_RSVD2 = 0x8001,
|
||||
PMUX_FUNC_RSVD3 = 0x8002,
|
||||
PMUX_FUNC_RSVD4 = 0x8003,
|
||||
};
|
||||
|
||||
/* return 1 if a pmux_func is in range */
|
||||
#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
|
||||
|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
|
||||
|
||||
/* return 1 if a pingrp is in range */
|
||||
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
|
||||
|
||||
/* The pullup/pulldown state of a pin group */
|
||||
enum pmux_pull {
|
||||
PMUX_PULL_NORMAL = 0,
|
||||
PMUX_PULL_DOWN,
|
||||
PMUX_PULL_UP,
|
||||
};
|
||||
/* return 1 if a pin_pupd_is in range */
|
||||
#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
|
||||
((pupd) <= PMUX_PULL_UP))
|
||||
|
||||
/* Defines whether a pin group is tristated or in normal operation */
|
||||
enum pmux_tristate {
|
||||
PMUX_TRI_NORMAL = 0,
|
||||
PMUX_TRI_TRISTATE = 1,
|
||||
};
|
||||
/* return 1 if a pin_tristate_is in range */
|
||||
#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
|
||||
&& ((tristate) <= PMUX_TRI_TRISTATE))
|
||||
|
||||
enum pmux_pin_io {
|
||||
PMUX_PIN_OUTPUT = 0,
|
||||
PMUX_PIN_INPUT = 1,
|
||||
};
|
||||
/* return 1 if a pin_io_is in range */
|
||||
#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
|
||||
((io) <= PMUX_PIN_INPUT))
|
||||
|
||||
enum pmux_pin_lock {
|
||||
PMUX_PIN_LOCK_DEFAULT = 0,
|
||||
PMUX_PIN_LOCK_DISABLE,
|
||||
PMUX_PIN_LOCK_ENABLE,
|
||||
};
|
||||
/* return 1 if a pin_lock is in range */
|
||||
#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
|
||||
((lock) <= PMUX_PIN_LOCK_ENABLE))
|
||||
|
||||
enum pmux_pin_od {
|
||||
PMUX_PIN_OD_DEFAULT = 0,
|
||||
PMUX_PIN_OD_DISABLE,
|
||||
PMUX_PIN_OD_ENABLE,
|
||||
};
|
||||
/* return 1 if a pin_od is in range */
|
||||
#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
|
||||
((od) <= PMUX_PIN_OD_ENABLE))
|
||||
|
||||
enum pmux_pin_ioreset {
|
||||
PMUX_PIN_IO_RESET_DEFAULT = 0,
|
||||
PMUX_PIN_IO_RESET_DISABLE,
|
||||
PMUX_PIN_IO_RESET_ENABLE,
|
||||
};
|
||||
/* return 1 if a pin_ioreset_is in range */
|
||||
#define pmux_pin_ioreset_isvalid(ioreset) \
|
||||
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
|
||||
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
|
||||
|
||||
/* Available power domains used by pin groups */
|
||||
enum pmux_vddio {
|
||||
PMUX_VDDIO_BB = 0,
|
||||
PMUX_VDDIO_LCD,
|
||||
PMUX_VDDIO_VI,
|
||||
PMUX_VDDIO_UART,
|
||||
PMUX_VDDIO_DDR,
|
||||
PMUX_VDDIO_NAND,
|
||||
PMUX_VDDIO_SYS,
|
||||
PMUX_VDDIO_AUDIO,
|
||||
PMUX_VDDIO_SD,
|
||||
PMUX_VDDIO_CAM,
|
||||
PMUX_VDDIO_GMI,
|
||||
PMUX_VDDIO_PEXCTL,
|
||||
PMUX_VDDIO_SDMMC1,
|
||||
PMUX_VDDIO_SDMMC3,
|
||||
PMUX_VDDIO_SDMMC4,
|
||||
|
||||
PMUX_VDDIO_NONE
|
||||
};
|
||||
|
||||
/* T114 pin drive group and pin mux registers */
|
||||
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
|
||||
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
|
||||
PDRIVE_PINGROUP_COUNT)
|
||||
struct pmux_tri_ctlr {
|
||||
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
|
||||
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
|
||||
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
|
||||
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
|
||||
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
|
||||
uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
|
||||
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
|
||||
|
||||
uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
|
||||
|
||||
uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
|
||||
uint pmt_reserved5[PMUX_OFFSET];
|
||||
uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
|
||||
};
|
||||
|
||||
/*
|
||||
* This defines the configuration for a pin, including the function assigned,
|
||||
* pull up/down settings and tristate settings. Having set up one of these
|
||||
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
|
||||
* available is pinmux_config_table() to configure a list of pins.
|
||||
*/
|
||||
struct pingroup_config {
|
||||
enum pmux_pingrp pingroup; /* pin group PINGRP_... */
|
||||
enum pmux_func func; /* function to assign FUNC_... */
|
||||
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
|
||||
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
|
||||
enum pmux_pin_io io; /* input or output PMUX_PIN_... */
|
||||
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
|
||||
enum pmux_pin_od od; /* open-drain or push-pull driver */
|
||||
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
|
||||
};
|
||||
|
||||
/* Set a pin group to tristate */
|
||||
void pinmux_tristate_enable(enum pmux_pingrp pin);
|
||||
|
||||
/* Set a pin group to normal (non tristate) */
|
||||
void pinmux_tristate_disable(enum pmux_pingrp pin);
|
||||
|
||||
/* Set the pull up/down feature for a pin group */
|
||||
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
|
||||
|
||||
/* Set the mux function for a pin group */
|
||||
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
|
||||
|
||||
/* Set the complete configuration for a pin group */
|
||||
void pinmux_config_pingroup(struct pingroup_config *config);
|
||||
|
||||
/* Set a pin group to tristate or normal */
|
||||
void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
|
||||
|
||||
/* Set a pin group as input or output */
|
||||
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
|
||||
|
||||
/**
|
||||
* Configure a list of pin groups
|
||||
*
|
||||
* @param config List of config items
|
||||
* @param len Number of config items in list
|
||||
*/
|
||||
void pinmux_config_table(struct pingroup_config *config, int len);
|
||||
|
||||
/* Set a group of pins from a table */
|
||||
void pinmux_init(void);
|
||||
|
||||
#endif /* _TEGRA114_PINMUX_H_ */
|
23
arch/arm/include/asm/arch-tegra114/pmu.h
Normal file
23
arch/arm/include/asm/arch-tegra114/pmu.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_PMU_H_
|
||||
#define _TEGRA114_PMU_H_
|
||||
|
||||
/* Set core and CPU voltages to nominal levels */
|
||||
int pmu_set_nominal(void);
|
||||
|
||||
#endif /* _TEGRA114_PMU_H_ */
|
22
arch/arm/include/asm/arch-tegra114/spl.h
Normal file
22
arch/arm/include/asm/arch-tegra114/spl.h
Normal file
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_RAM 1
|
||||
|
||||
#endif
|
33
arch/arm/include/asm/arch-tegra114/tegra.h
Normal file
33
arch/arm/include/asm/arch-tegra114/tegra.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA114_H_
|
||||
#define _TEGRA114_H_
|
||||
|
||||
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
|
||||
|
||||
#include <asm/arch-tegra/tegra.h>
|
||||
|
||||
#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */
|
||||
|
||||
#undef NVBOOTINFOTABLE_BCTSIZE
|
||||
#undef NVBOOTINFOTABLE_BCTPTR
|
||||
#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
|
||||
#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
|
||||
|
||||
#define MAX_NUM_CPU 4
|
||||
|
||||
#endif /* TEGRA114_H */
|
@@ -193,4 +193,8 @@ enum pll_out_id {
|
||||
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
|
||||
(id) < CLOCK_ID_FIRST_SIMPLE)
|
||||
|
||||
/* return 1 if a peripheral ID is in range */
|
||||
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
|
||||
(id) < PERIPH_ID_COUNT)
|
||||
|
||||
#endif /* _CLOCK_TABLES_H_ */
|
||||
|
@@ -26,4 +26,8 @@
|
||||
|
||||
#include <asm/arch-tegra/clock.h>
|
||||
|
||||
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
|
||||
#define OSC_FREQ_SHIFT 30
|
||||
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
|
||||
|
||||
#endif /* _TEGRA20_CLOCK_H */
|
||||
|
@@ -21,8 +21,10 @@
|
||||
|
||||
/* Tegra20 high-level function multiplexing */
|
||||
|
||||
#ifndef __FUNCMUX_H
|
||||
#define __FUNCMUX_H
|
||||
#ifndef _TEGRA20_FUNCMUX_H_
|
||||
#define _TEGRA20_FUNCMUX_H_
|
||||
|
||||
#include <asm/arch-tegra/funcmux.h>
|
||||
|
||||
/* Configs supported by the func mux */
|
||||
enum {
|
||||
@@ -33,7 +35,7 @@ enum {
|
||||
FUNCMUX_UART1_UAA_UAB,
|
||||
FUNCMUX_UART1_GPU,
|
||||
FUNCMUX_UART1_SDIO1,
|
||||
FUNCMUX_UART2_IRDA = 0,
|
||||
FUNCMUX_UART2_UAD = 0,
|
||||
FUNCMUX_UART4_GMC = 0,
|
||||
|
||||
/* I2C configs */
|
||||
@@ -62,22 +64,4 @@ enum {
|
||||
FUNCMUX_NDFLASH_ATC = 0,
|
||||
FUNCMUX_NDFLASH_KBC_8_BIT,
|
||||
};
|
||||
|
||||
/**
|
||||
* Select a config for a particular peripheral.
|
||||
*
|
||||
* Each peripheral can operate through a number of configurations,
|
||||
* which are sets of pins that it uses to bring out its signals.
|
||||
* The basic config is 0, and higher numbers indicate different
|
||||
* pinmux settings to bring the peripheral out on other pins,
|
||||
*
|
||||
* This function also disables tristate for the function's pins,
|
||||
* so that they operate in normal mode.
|
||||
*
|
||||
* @param id Peripheral id
|
||||
* @param config Configuration to use (FUNCMUX_...), 0 for default
|
||||
* @return 0 if ok, -1 on error (e.g. incorrect id or config)
|
||||
*/
|
||||
int funcmux_select(enum periph_id id, int config);
|
||||
|
||||
#endif
|
||||
#endif /* _TEGRA20_FUNCMUX_H_ */
|
||||
|
@@ -21,8 +21,10 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _GP_PADCTRL_H_
|
||||
#define _GP_PADCTRL_H_
|
||||
#ifndef _TEGRA20_GP_PADCTRL_H_
|
||||
#define _TEGRA20_GP_PADCTRL_H_
|
||||
|
||||
#include <asm/arch-tegra/gp_padctrl.h>
|
||||
|
||||
/* APB_MISC_GP and padctrl registers */
|
||||
struct apb_misc_gp_ctlr {
|
||||
@@ -61,13 +63,4 @@ struct apb_misc_gp_ctlr {
|
||||
u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
|
||||
};
|
||||
|
||||
/* bit fields definitions for APB_MISC_GP_HIDREV register */
|
||||
#define HIDREV_CHIPID_SHIFT 8
|
||||
#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
|
||||
#define HIDREV_MAJORPREV_SHIFT 4
|
||||
#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
|
||||
|
||||
/* CHIPID field returned from APB_MISC_GP_HIDREV register */
|
||||
#define CHIPID_TEGRA20 0x20
|
||||
|
||||
#endif
|
||||
#endif /* _TEGRA20_GP_PADCTRL_H_ */
|
||||
|
@@ -204,7 +204,6 @@ enum pmux_func {
|
||||
PMUX_FUNC_I2C2,
|
||||
PMUX_FUNC_I2C3,
|
||||
PMUX_FUNC_IDE,
|
||||
PMUX_FUNC_IRDA,
|
||||
PMUX_FUNC_KBC,
|
||||
PMUX_FUNC_MIO,
|
||||
PMUX_FUNC_MIPI_HS,
|
||||
|
@@ -33,4 +33,6 @@
|
||||
|
||||
#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
|
||||
|
||||
#define MAX_NUM_CPU 2
|
||||
|
||||
#endif /* TEGRA20_H */
|
||||
|
382
arch/arm/include/asm/arch-tegra30/clock-tables.h
Normal file
382
arch/arm/include/asm/arch-tegra30/clock-tables.h
Normal file
@@ -0,0 +1,382 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra30 clock PLL tables */
|
||||
|
||||
#ifndef _TEGRA30_CLOCK_TABLES_H_
|
||||
#define _TEGRA30_CLOCK_TABLES_H_
|
||||
|
||||
/* The PLLs supported by the hardware */
|
||||
enum clock_id {
|
||||
CLOCK_ID_FIRST,
|
||||
CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
|
||||
CLOCK_ID_MEMORY,
|
||||
CLOCK_ID_PERIPH,
|
||||
CLOCK_ID_AUDIO,
|
||||
CLOCK_ID_USB,
|
||||
CLOCK_ID_DISPLAY,
|
||||
|
||||
/* now the simple ones */
|
||||
CLOCK_ID_FIRST_SIMPLE,
|
||||
CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
|
||||
CLOCK_ID_EPCI,
|
||||
CLOCK_ID_SFROM32KHZ,
|
||||
|
||||
/* These are the base clocks (inputs to the Tegra SOC) */
|
||||
CLOCK_ID_32KHZ,
|
||||
CLOCK_ID_OSC,
|
||||
|
||||
CLOCK_ID_COUNT, /* number of PLLs */
|
||||
CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
|
||||
CLOCK_ID_NONE = -1,
|
||||
};
|
||||
|
||||
/* The clocks supported by the hardware */
|
||||
enum periph_id {
|
||||
PERIPH_ID_FIRST,
|
||||
|
||||
/* Low word: 31:0 */
|
||||
PERIPH_ID_CPU = PERIPH_ID_FIRST,
|
||||
PERIPH_ID_COP,
|
||||
PERIPH_ID_TRIGSYS,
|
||||
PERIPH_ID_RESERVED3,
|
||||
PERIPH_ID_RESERVED4,
|
||||
PERIPH_ID_TMR,
|
||||
PERIPH_ID_UART1,
|
||||
PERIPH_ID_UART2,
|
||||
|
||||
/* 8 */
|
||||
PERIPH_ID_GPIO,
|
||||
PERIPH_ID_SDMMC2,
|
||||
PERIPH_ID_SPDIF,
|
||||
PERIPH_ID_I2S1,
|
||||
PERIPH_ID_I2C1,
|
||||
PERIPH_ID_NDFLASH,
|
||||
PERIPH_ID_SDMMC1,
|
||||
PERIPH_ID_SDMMC4,
|
||||
|
||||
/* 16 */
|
||||
PERIPH_ID_RESERVED16,
|
||||
PERIPH_ID_PWM,
|
||||
PERIPH_ID_I2S2,
|
||||
PERIPH_ID_EPP,
|
||||
PERIPH_ID_VI,
|
||||
PERIPH_ID_2D,
|
||||
PERIPH_ID_USBD,
|
||||
PERIPH_ID_ISP,
|
||||
|
||||
/* 24 */
|
||||
PERIPH_ID_3D,
|
||||
PERIPH_ID_RESERVED24,
|
||||
PERIPH_ID_DISP2,
|
||||
PERIPH_ID_DISP1,
|
||||
PERIPH_ID_HOST1X,
|
||||
PERIPH_ID_VCP,
|
||||
PERIPH_ID_I2S0,
|
||||
PERIPH_ID_CACHE2,
|
||||
|
||||
/* Middle word: 63:32 */
|
||||
PERIPH_ID_MEM,
|
||||
PERIPH_ID_AHBDMA,
|
||||
PERIPH_ID_APBDMA,
|
||||
PERIPH_ID_RESERVED35,
|
||||
PERIPH_ID_KBC,
|
||||
PERIPH_ID_STAT_MON,
|
||||
PERIPH_ID_PMC,
|
||||
PERIPH_ID_FUSE,
|
||||
|
||||
/* 40 */
|
||||
PERIPH_ID_KFUSE,
|
||||
PERIPH_ID_SBC1,
|
||||
PERIPH_ID_SNOR,
|
||||
PERIPH_ID_RESERVED43,
|
||||
PERIPH_ID_SBC2,
|
||||
PERIPH_ID_RESERVED45,
|
||||
PERIPH_ID_SBC3,
|
||||
PERIPH_ID_DVC_I2C,
|
||||
|
||||
/* 48 */
|
||||
PERIPH_ID_DSI,
|
||||
PERIPH_ID_TVO,
|
||||
PERIPH_ID_MIPI,
|
||||
PERIPH_ID_HDMI,
|
||||
PERIPH_ID_CSI,
|
||||
PERIPH_ID_TVDAC,
|
||||
PERIPH_ID_I2C2,
|
||||
PERIPH_ID_UART3,
|
||||
|
||||
/* 56 */
|
||||
PERIPH_ID_RESERVED56,
|
||||
PERIPH_ID_EMC,
|
||||
PERIPH_ID_USB2,
|
||||
PERIPH_ID_USB3,
|
||||
PERIPH_ID_MPE,
|
||||
PERIPH_ID_VDE,
|
||||
PERIPH_ID_BSEA,
|
||||
PERIPH_ID_BSEV,
|
||||
|
||||
/* Upper word 95:64 */
|
||||
PERIPH_ID_SPEEDO,
|
||||
PERIPH_ID_UART4,
|
||||
PERIPH_ID_UART5,
|
||||
PERIPH_ID_I2C3,
|
||||
PERIPH_ID_SBC4,
|
||||
PERIPH_ID_SDMMC3,
|
||||
PERIPH_ID_PCIE,
|
||||
PERIPH_ID_OWR,
|
||||
|
||||
/* 72 */
|
||||
PERIPH_ID_AFI,
|
||||
PERIPH_ID_CORESIGHT,
|
||||
PERIPH_ID_PCIEXCLK,
|
||||
PERIPH_ID_AVPUCQ,
|
||||
PERIPH_ID_RESERVED76,
|
||||
PERIPH_ID_RESERVED77,
|
||||
PERIPH_ID_RESERVED78,
|
||||
PERIPH_ID_DTV,
|
||||
|
||||
/* 80 */
|
||||
PERIPH_ID_NANDSPEED,
|
||||
PERIPH_ID_I2CSLOW,
|
||||
PERIPH_ID_DSIB,
|
||||
PERIPH_ID_RESERVED83,
|
||||
PERIPH_ID_IRAMA,
|
||||
PERIPH_ID_IRAMB,
|
||||
PERIPH_ID_IRAMC,
|
||||
PERIPH_ID_IRAMD,
|
||||
|
||||
/* 88 */
|
||||
PERIPH_ID_CRAM2,
|
||||
PERIPH_ID_RESERVED89,
|
||||
PERIPH_ID_MDOUBLER,
|
||||
PERIPH_ID_RESERVED91,
|
||||
PERIPH_ID_SUSOUT,
|
||||
PERIPH_ID_RESERVED93,
|
||||
PERIPH_ID_RESERVED94,
|
||||
PERIPH_ID_RESERVED95,
|
||||
|
||||
PERIPH_ID_VW_FIRST,
|
||||
/* V word: 31:0 */
|
||||
PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
|
||||
PERIPH_ID_CPULP,
|
||||
PERIPH_ID_3D2,
|
||||
PERIPH_ID_MSELECT,
|
||||
PERIPH_ID_TSENSOR,
|
||||
PERIPH_ID_I2S3,
|
||||
PERIPH_ID_I2S4,
|
||||
PERIPH_ID_I2C4,
|
||||
|
||||
/* 08 */
|
||||
PERIPH_ID_SBC5,
|
||||
PERIPH_ID_SBC6,
|
||||
PERIPH_ID_AUDIO,
|
||||
PERIPH_ID_APBIF,
|
||||
PERIPH_ID_DAM0,
|
||||
PERIPH_ID_DAM1,
|
||||
PERIPH_ID_DAM2,
|
||||
PERIPH_ID_HDA2CODEC2X,
|
||||
|
||||
/* 16 */
|
||||
PERIPH_ID_ATOMICS,
|
||||
PERIPH_ID_EX_RESERVED17,
|
||||
PERIPH_ID_EX_RESERVED18,
|
||||
PERIPH_ID_EX_RESERVED19,
|
||||
PERIPH_ID_EX_RESERVED20,
|
||||
PERIPH_ID_EX_RESERVED21,
|
||||
PERIPH_ID_EX_RESERVED22,
|
||||
PERIPH_ID_ACTMON,
|
||||
|
||||
/* 24 */
|
||||
PERIPH_ID_EX_RESERVED24,
|
||||
PERIPH_ID_EX_RESERVED25,
|
||||
PERIPH_ID_EX_RESERVED26,
|
||||
PERIPH_ID_EX_RESERVED27,
|
||||
PERIPH_ID_SATA,
|
||||
PERIPH_ID_HDA,
|
||||
PERIPH_ID_EX_RESERVED30,
|
||||
PERIPH_ID_EX_RESERVED31,
|
||||
|
||||
/* W word: 31:0 */
|
||||
PERIPH_ID_HDA2HDMICODEC,
|
||||
PERIPH_ID_SATACOLD,
|
||||
PERIPH_ID_RESERVED0_PCIERX0,
|
||||
PERIPH_ID_RESERVED1_PCIERX1,
|
||||
PERIPH_ID_RESERVED2_PCIERX2,
|
||||
PERIPH_ID_RESERVED3_PCIERX3,
|
||||
PERIPH_ID_RESERVED4_PCIERX4,
|
||||
PERIPH_ID_RESERVED5_PCIERX5,
|
||||
|
||||
/* 40 */
|
||||
PERIPH_ID_CEC,
|
||||
PERIPH_ID_RESERVED6_PCIE2,
|
||||
PERIPH_ID_RESERVED7_EMC,
|
||||
PERIPH_ID_RESERVED8_HDMI,
|
||||
PERIPH_ID_RESERVED9_SATA,
|
||||
PERIPH_ID_RESERVED10_MIPI,
|
||||
PERIPH_ID_EX_RESERVED46,
|
||||
PERIPH_ID_EX_RESERVED47,
|
||||
|
||||
PERIPH_ID_COUNT,
|
||||
PERIPH_ID_NONE = -1,
|
||||
};
|
||||
|
||||
enum pll_out_id {
|
||||
PLL_OUT1,
|
||||
PLL_OUT2,
|
||||
PLL_OUT3,
|
||||
PLL_OUT4
|
||||
};
|
||||
|
||||
/*
|
||||
* Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
|
||||
* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
|
||||
* confusion bewteen PERIPH_ID_... and PERIPHC_...
|
||||
*
|
||||
* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
|
||||
* confusing.
|
||||
*/
|
||||
enum periphc_internal_id {
|
||||
/* 0x00 */
|
||||
PERIPHC_I2S1,
|
||||
PERIPHC_I2S2,
|
||||
PERIPHC_SPDIF_OUT,
|
||||
PERIPHC_SPDIF_IN,
|
||||
PERIPHC_PWM,
|
||||
PERIPHC_05h,
|
||||
PERIPHC_SBC2,
|
||||
PERIPHC_SBC3,
|
||||
|
||||
/* 0x08 */
|
||||
PERIPHC_08h,
|
||||
PERIPHC_I2C1,
|
||||
PERIPHC_DVC_I2C,
|
||||
PERIPHC_0bh,
|
||||
PERIPHC_0ch,
|
||||
PERIPHC_SBC1,
|
||||
PERIPHC_DISP1,
|
||||
PERIPHC_DISP2,
|
||||
|
||||
/* 0x10 */
|
||||
PERIPHC_CVE,
|
||||
PERIPHC_11h,
|
||||
PERIPHC_VI,
|
||||
PERIPHC_13h,
|
||||
PERIPHC_SDMMC1,
|
||||
PERIPHC_SDMMC2,
|
||||
PERIPHC_G3D,
|
||||
PERIPHC_G2D,
|
||||
|
||||
/* 0x18 */
|
||||
PERIPHC_NDFLASH,
|
||||
PERIPHC_SDMMC4,
|
||||
PERIPHC_VFIR,
|
||||
PERIPHC_EPP,
|
||||
PERIPHC_MPE,
|
||||
PERIPHC_MIPI,
|
||||
PERIPHC_UART1,
|
||||
PERIPHC_UART2,
|
||||
|
||||
/* 0x20 */
|
||||
PERIPHC_HOST1X,
|
||||
PERIPHC_21h,
|
||||
PERIPHC_TVO,
|
||||
PERIPHC_HDMI,
|
||||
PERIPHC_24h,
|
||||
PERIPHC_TVDAC,
|
||||
PERIPHC_I2C2,
|
||||
PERIPHC_EMC,
|
||||
|
||||
/* 0x28 */
|
||||
PERIPHC_UART3,
|
||||
PERIPHC_29h,
|
||||
PERIPHC_VI_SENSOR,
|
||||
PERIPHC_2bh,
|
||||
PERIPHC_2ch,
|
||||
PERIPHC_SBC4,
|
||||
PERIPHC_I2C3,
|
||||
PERIPHC_SDMMC3,
|
||||
|
||||
/* 0x30 */
|
||||
PERIPHC_UART4,
|
||||
PERIPHC_UART5,
|
||||
PERIPHC_VDE,
|
||||
PERIPHC_OWR,
|
||||
PERIPHC_NOR,
|
||||
PERIPHC_CSITE,
|
||||
PERIPHC_I2S0,
|
||||
PERIPHC_37h,
|
||||
|
||||
PERIPHC_VW_FIRST,
|
||||
/* 0x38 */
|
||||
PERIPHC_G3D2 = PERIPHC_VW_FIRST,
|
||||
PERIPHC_MSELECT,
|
||||
PERIPHC_TSENSOR,
|
||||
PERIPHC_I2S3,
|
||||
PERIPHC_I2S4,
|
||||
PERIPHC_I2C4,
|
||||
PERIPHC_SBC5,
|
||||
PERIPHC_SBC6,
|
||||
|
||||
/* 0x40 */
|
||||
PERIPHC_AUDIO,
|
||||
PERIPHC_41h,
|
||||
PERIPHC_DAM0,
|
||||
PERIPHC_DAM1,
|
||||
PERIPHC_DAM2,
|
||||
PERIPHC_HDA2CODEC2X,
|
||||
PERIPHC_ACTMON,
|
||||
PERIPHC_EXTPERIPH1,
|
||||
|
||||
/* 0x48 */
|
||||
PERIPHC_EXTPERIPH2,
|
||||
PERIPHC_EXTPERIPH3,
|
||||
PERIPHC_NANDSPEED,
|
||||
PERIPHC_I2CSLOW,
|
||||
PERIPHC_SYS,
|
||||
PERIPHC_SPEEDO,
|
||||
PERIPHC_4eh,
|
||||
PERIPHC_4fh,
|
||||
|
||||
/* 0x50 */
|
||||
PERIPHC_50h,
|
||||
PERIPHC_51h,
|
||||
PERIPHC_52h,
|
||||
PERIPHC_53h,
|
||||
PERIPHC_SATAOOB,
|
||||
PERIPHC_SATA,
|
||||
PERIPHC_HDA,
|
||||
|
||||
PERIPHC_COUNT,
|
||||
|
||||
PERIPHC_NONE = -1,
|
||||
};
|
||||
|
||||
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
|
||||
#define PERIPH_REG(id) \
|
||||
(id < PERIPH_ID_VW_FIRST) ? \
|
||||
((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
|
||||
|
||||
/* Mask value for a clock (within PERIPH_REG(id)) */
|
||||
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
|
||||
|
||||
/* return 1 if a PLL ID is in range */
|
||||
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
|
||||
|
||||
/* return 1 if a peripheral ID is in range */
|
||||
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
|
||||
(id) < PERIPH_ID_COUNT)
|
||||
|
||||
#endif /* _TEGRA30_CLOCK_TABLES_H_ */
|
28
arch/arm/include/asm/arch-tegra30/clock.h
Normal file
28
arch/arm/include/asm/arch-tegra30/clock.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra30 clock control functions */
|
||||
|
||||
#ifndef _TEGRA30_CLOCK_H_
|
||||
#define _TEGRA30_CLOCK_H_
|
||||
|
||||
#include <asm/arch-tegra/clock.h>
|
||||
|
||||
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
|
||||
#define OSC_FREQ_SHIFT 28
|
||||
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
|
||||
|
||||
#endif /* _TEGRA30_CLOCK_H_ */
|
35
arch/arm/include/asm/arch-tegra30/flow.h
Normal file
35
arch/arm/include/asm/arch-tegra30/flow.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_FLOW_H_
|
||||
#define _TEGRA30_FLOW_H_
|
||||
|
||||
struct flow_ctlr {
|
||||
u32 halt_cpu_events;
|
||||
u32 halt_cop_events;
|
||||
u32 cpu_csr;
|
||||
u32 cop_csr;
|
||||
u32 xrq_events;
|
||||
u32 halt_cpu1_events;
|
||||
u32 cpu1_csr;
|
||||
u32 halt_cpu2_events;
|
||||
u32 cpu2_csr;
|
||||
u32 halt_cpu3_events;
|
||||
u32 cpu3_csr;
|
||||
u32 cluster_control;
|
||||
};
|
||||
|
||||
#endif /* _TEGRA30_FLOW_H_ */
|
31
arch/arm/include/asm/arch-tegra30/funcmux.h
Normal file
31
arch/arm/include/asm/arch-tegra30/funcmux.h
Normal file
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* Tegra30 high-level function multiplexing */
|
||||
|
||||
#ifndef _TEGRA30_FUNCMUX_H_
|
||||
#define _TEGRA30_FUNCMUX_H_
|
||||
|
||||
#include <asm/arch-tegra/funcmux.h>
|
||||
|
||||
/* Configs supported by the func mux */
|
||||
enum {
|
||||
FUNCMUX_DEFAULT = 0, /* default config */
|
||||
|
||||
/* UART configs */
|
||||
FUNCMUX_UART1_ULPI = 0,
|
||||
};
|
||||
#endif /* _TEGRA30_FUNCMUX_H_ */
|
59
arch/arm/include/asm/arch-tegra30/gp_padctrl.h
Normal file
59
arch/arm/include/asm/arch-tegra30/gp_padctrl.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_GP_PADCTRL_H_
|
||||
#define _TEGRA30_GP_PADCTRL_H_
|
||||
|
||||
#include <asm/arch-tegra/gp_padctrl.h>
|
||||
|
||||
/* APB_MISC_GP and padctrl registers */
|
||||
struct apb_misc_gp_ctlr {
|
||||
u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
|
||||
u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
|
||||
u32 reserved0[22]; /* 0x08 - 0x5C: */
|
||||
u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
|
||||
u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
|
||||
u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
|
||||
u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
|
||||
u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
|
||||
u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
|
||||
u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
|
||||
u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
|
||||
u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
|
||||
u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
|
||||
u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
|
||||
u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
|
||||
u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
|
||||
u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
|
||||
u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
|
||||
u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
|
||||
u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
|
||||
u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
|
||||
u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
|
||||
u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
|
||||
u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
|
||||
u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
|
||||
u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
|
||||
u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
|
||||
u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
|
||||
u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
|
||||
u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
|
||||
u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
|
||||
u32 reserved1[7]; /* 0xD0-0xE8: */
|
||||
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
|
||||
};
|
||||
|
||||
#endif /* _TEGRA30_GP_PADCTRL_H_ */
|
304
arch/arm/include/asm/arch-tegra30/gpio.h
Normal file
304
arch/arm/include/asm/arch-tegra30/gpio.h
Normal file
@@ -0,0 +1,304 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_GPIO_H_
|
||||
#define _TEGRA30_GPIO_H_
|
||||
|
||||
/*
|
||||
* The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
|
||||
* each with 8 GPIOs.
|
||||
*/
|
||||
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
|
||||
#define TEGRA_GPIO_BANKS 8 /* number of banks */
|
||||
|
||||
#include <asm/arch-tegra/gpio.h>
|
||||
|
||||
/* GPIO Controller registers for a single bank */
|
||||
struct gpio_ctlr_bank {
|
||||
uint gpio_config[TEGRA_GPIO_PORTS];
|
||||
uint gpio_dir_out[TEGRA_GPIO_PORTS];
|
||||
uint gpio_out[TEGRA_GPIO_PORTS];
|
||||
uint gpio_in[TEGRA_GPIO_PORTS];
|
||||
uint gpio_int_status[TEGRA_GPIO_PORTS];
|
||||
uint gpio_int_enable[TEGRA_GPIO_PORTS];
|
||||
uint gpio_int_level[TEGRA_GPIO_PORTS];
|
||||
uint gpio_int_clear[TEGRA_GPIO_PORTS];
|
||||
uint gpio_masked_config[TEGRA_GPIO_PORTS];
|
||||
uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
|
||||
uint gpio_masked_out[TEGRA_GPIO_PORTS];
|
||||
uint gpio_masked_in[TEGRA_GPIO_PORTS];
|
||||
uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
|
||||
uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
|
||||
uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
|
||||
uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
|
||||
};
|
||||
|
||||
struct gpio_ctlr {
|
||||
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
|
||||
};
|
||||
|
||||
enum gpio_pin {
|
||||
GPIO_PA0 = 0, /* pin 0 */
|
||||
GPIO_PA1,
|
||||
GPIO_PA2,
|
||||
GPIO_PA3,
|
||||
GPIO_PA4,
|
||||
GPIO_PA5,
|
||||
GPIO_PA6,
|
||||
GPIO_PA7,
|
||||
GPIO_PB0, /* pin 8 */
|
||||
GPIO_PB1,
|
||||
GPIO_PB2,
|
||||
GPIO_PB3,
|
||||
GPIO_PB4,
|
||||
GPIO_PB5,
|
||||
GPIO_PB6,
|
||||
GPIO_PB7,
|
||||
GPIO_PC0, /* pin 16 */
|
||||
GPIO_PC1,
|
||||
GPIO_PC2,
|
||||
GPIO_PC3,
|
||||
GPIO_PC4,
|
||||
GPIO_PC5,
|
||||
GPIO_PC6,
|
||||
GPIO_PC7,
|
||||
GPIO_PD0, /* pin 24 */
|
||||
GPIO_PD1,
|
||||
GPIO_PD2,
|
||||
GPIO_PD3,
|
||||
GPIO_PD4,
|
||||
GPIO_PD5,
|
||||
GPIO_PD6,
|
||||
GPIO_PD7,
|
||||
GPIO_PE0, /* pin 32 */
|
||||
GPIO_PE1,
|
||||
GPIO_PE2,
|
||||
GPIO_PE3,
|
||||
GPIO_PE4,
|
||||
GPIO_PE5,
|
||||
GPIO_PE6,
|
||||
GPIO_PE7,
|
||||
GPIO_PF0, /* pin 40 */
|
||||
GPIO_PF1,
|
||||
GPIO_PF2,
|
||||
GPIO_PF3,
|
||||
GPIO_PF4,
|
||||
GPIO_PF5,
|
||||
GPIO_PF6,
|
||||
GPIO_PF7,
|
||||
GPIO_PG0, /* pin 48 */
|
||||
GPIO_PG1,
|
||||
GPIO_PG2,
|
||||
GPIO_PG3,
|
||||
GPIO_PG4,
|
||||
GPIO_PG5,
|
||||
GPIO_PG6,
|
||||
GPIO_PG7,
|
||||
GPIO_PH0, /* pin 56 */
|
||||
GPIO_PH1,
|
||||
GPIO_PH2,
|
||||
GPIO_PH3,
|
||||
GPIO_PH4,
|
||||
GPIO_PH5,
|
||||
GPIO_PH6,
|
||||
GPIO_PH7,
|
||||
GPIO_PI0, /* pin 64 */
|
||||
GPIO_PI1,
|
||||
GPIO_PI2,
|
||||
GPIO_PI3,
|
||||
GPIO_PI4,
|
||||
GPIO_PI5,
|
||||
GPIO_PI6,
|
||||
GPIO_PI7,
|
||||
GPIO_PJ0, /* pin 72 */
|
||||
GPIO_PJ1,
|
||||
GPIO_PJ2,
|
||||
GPIO_PJ3,
|
||||
GPIO_PJ4,
|
||||
GPIO_PJ5,
|
||||
GPIO_PJ6,
|
||||
GPIO_PJ7,
|
||||
GPIO_PK0, /* pin 80 */
|
||||
GPIO_PK1,
|
||||
GPIO_PK2,
|
||||
GPIO_PK3,
|
||||
GPIO_PK4,
|
||||
GPIO_PK5,
|
||||
GPIO_PK6,
|
||||
GPIO_PK7,
|
||||
GPIO_PL0, /* pin 88 */
|
||||
GPIO_PL1,
|
||||
GPIO_PL2,
|
||||
GPIO_PL3,
|
||||
GPIO_PL4,
|
||||
GPIO_PL5,
|
||||
GPIO_PL6,
|
||||
GPIO_PL7,
|
||||
GPIO_PM0, /* pin 96 */
|
||||
GPIO_PM1,
|
||||
GPIO_PM2,
|
||||
GPIO_PM3,
|
||||
GPIO_PM4,
|
||||
GPIO_PM5,
|
||||
GPIO_PM6,
|
||||
GPIO_PM7,
|
||||
GPIO_PN0, /* pin 104 */
|
||||
GPIO_PN1,
|
||||
GPIO_PN2,
|
||||
GPIO_PN3,
|
||||
GPIO_PN4,
|
||||
GPIO_PN5,
|
||||
GPIO_PN6,
|
||||
GPIO_PN7,
|
||||
GPIO_PO0, /* pin 112 */
|
||||
GPIO_PO1,
|
||||
GPIO_PO2,
|
||||
GPIO_PO3,
|
||||
GPIO_PO4,
|
||||
GPIO_PO5,
|
||||
GPIO_PO6,
|
||||
GPIO_PO7,
|
||||
GPIO_PP0, /* pin 120 */
|
||||
GPIO_PP1,
|
||||
GPIO_PP2,
|
||||
GPIO_PP3,
|
||||
GPIO_PP4,
|
||||
GPIO_PP5,
|
||||
GPIO_PP6,
|
||||
GPIO_PP7,
|
||||
GPIO_PQ0, /* pin 128 */
|
||||
GPIO_PQ1,
|
||||
GPIO_PQ2,
|
||||
GPIO_PQ3,
|
||||
GPIO_PQ4,
|
||||
GPIO_PQ5,
|
||||
GPIO_PQ6,
|
||||
GPIO_PQ7,
|
||||
GPIO_PR0, /* pin 136 */
|
||||
GPIO_PR1,
|
||||
GPIO_PR2,
|
||||
GPIO_PR3,
|
||||
GPIO_PR4,
|
||||
GPIO_PR5,
|
||||
GPIO_PR6,
|
||||
GPIO_PR7,
|
||||
GPIO_PS0, /* pin 144 */
|
||||
GPIO_PS1,
|
||||
GPIO_PS2,
|
||||
GPIO_PS3,
|
||||
GPIO_PS4,
|
||||
GPIO_PS5,
|
||||
GPIO_PS6,
|
||||
GPIO_PS7,
|
||||
GPIO_PT0, /* pin 152 */
|
||||
GPIO_PT1,
|
||||
GPIO_PT2,
|
||||
GPIO_PT3,
|
||||
GPIO_PT4,
|
||||
GPIO_PT5,
|
||||
GPIO_PT6,
|
||||
GPIO_PT7,
|
||||
GPIO_PU0, /* pin 160 */
|
||||
GPIO_PU1,
|
||||
GPIO_PU2,
|
||||
GPIO_PU3,
|
||||
GPIO_PU4,
|
||||
GPIO_PU5,
|
||||
GPIO_PU6,
|
||||
GPIO_PU7,
|
||||
GPIO_PV0, /* pin 168 */
|
||||
GPIO_PV1,
|
||||
GPIO_PV2,
|
||||
GPIO_PV3,
|
||||
GPIO_PV4,
|
||||
GPIO_PV5,
|
||||
GPIO_PV6,
|
||||
GPIO_PV7,
|
||||
GPIO_PW0, /* pin 176 */
|
||||
GPIO_PW1,
|
||||
GPIO_PW2,
|
||||
GPIO_PW3,
|
||||
GPIO_PW4,
|
||||
GPIO_PW5,
|
||||
GPIO_PW6,
|
||||
GPIO_PW7,
|
||||
GPIO_PX0, /* pin 184 */
|
||||
GPIO_PX1,
|
||||
GPIO_PX2,
|
||||
GPIO_PX3,
|
||||
GPIO_PX4,
|
||||
GPIO_PX5,
|
||||
GPIO_PX6,
|
||||
GPIO_PX7,
|
||||
GPIO_PY0, /* pin 192 */
|
||||
GPIO_PY1,
|
||||
GPIO_PY2,
|
||||
GPIO_PY3,
|
||||
GPIO_PY4,
|
||||
GPIO_PY5,
|
||||
GPIO_PY6,
|
||||
GPIO_PY7,
|
||||
GPIO_PZ0, /* pin 200 */
|
||||
GPIO_PZ1,
|
||||
GPIO_PZ2,
|
||||
GPIO_PZ3,
|
||||
GPIO_PZ4,
|
||||
GPIO_PZ5,
|
||||
GPIO_PZ6,
|
||||
GPIO_PZ7,
|
||||
GPIO_PAA0, /* pin 208 */
|
||||
GPIO_PAA1,
|
||||
GPIO_PAA2,
|
||||
GPIO_PAA3,
|
||||
GPIO_PAA4,
|
||||
GPIO_PAA5,
|
||||
GPIO_PAA6,
|
||||
GPIO_PAA7,
|
||||
GPIO_PBB0, /* pin 216 */
|
||||
GPIO_PBB1,
|
||||
GPIO_PBB2,
|
||||
GPIO_PBB3,
|
||||
GPIO_PBB4,
|
||||
GPIO_PBB5,
|
||||
GPIO_PBB6,
|
||||
GPIO_PBB7,
|
||||
GPIO_PCC0, /* pin 224 */
|
||||
GPIO_PCC1,
|
||||
GPIO_PCC2,
|
||||
GPIO_PCC3,
|
||||
GPIO_PCC4,
|
||||
GPIO_PCC5,
|
||||
GPIO_PCC6,
|
||||
GPIO_PCC7,
|
||||
GPIO_PDD0, /* pin 232 */
|
||||
GPIO_PDD1,
|
||||
GPIO_PDD2,
|
||||
GPIO_PDD3,
|
||||
GPIO_PDD4,
|
||||
GPIO_PDD5,
|
||||
GPIO_PDD6,
|
||||
GPIO_PDD7,
|
||||
GPIO_PEE0, /* pin 240 */
|
||||
GPIO_PEE1,
|
||||
GPIO_PEE2,
|
||||
GPIO_PEE3,
|
||||
GPIO_PEE4,
|
||||
GPIO_PEE5,
|
||||
GPIO_PEE6,
|
||||
GPIO_PEE7, /* pin 247 */
|
||||
};
|
||||
|
||||
#endif /* _TEGRA30_GPIO_H_ */
|
22
arch/arm/include/asm/arch-tegra30/hardware.h
Normal file
22
arch/arm/include/asm/arch-tegra30/hardware.h
Normal file
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_HARDWARE_H_
|
||||
#define _TEGRA30_HARDWARE_H_
|
||||
|
||||
/* include tegra specific hardware definitions */
|
||||
|
||||
#endif /* _TEGRA30-HARDWARE_H_ */
|
603
arch/arm/include/asm/arch-tegra30/pinmux.h
Normal file
603
arch/arm/include/asm/arch-tegra30/pinmux.h
Normal file
@@ -0,0 +1,603 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_PINMUX_H_
|
||||
#define _TEGRA30_PINMUX_H_
|
||||
|
||||
/*
|
||||
* Pin groups which we adjust. There are three basic attributes of each pin
|
||||
* group which use this enum:
|
||||
*
|
||||
* - function
|
||||
* - pullup / pulldown
|
||||
* - tristate or normal
|
||||
*/
|
||||
enum pmux_pingrp {
|
||||
PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
|
||||
PINGRP_ULPI_DATA1,
|
||||
PINGRP_ULPI_DATA2,
|
||||
PINGRP_ULPI_DATA3,
|
||||
PINGRP_ULPI_DATA4,
|
||||
PINGRP_ULPI_DATA5,
|
||||
PINGRP_ULPI_DATA6,
|
||||
PINGRP_ULPI_DATA7,
|
||||
PINGRP_ULPI_CLK,
|
||||
PINGRP_ULPI_DIR,
|
||||
PINGRP_ULPI_NXT,
|
||||
PINGRP_ULPI_STP,
|
||||
PINGRP_DAP3_FS,
|
||||
PINGRP_DAP3_DIN,
|
||||
PINGRP_DAP3_DOUT,
|
||||
PINGRP_DAP3_SCLK,
|
||||
PINGRP_GPIO_PV0,
|
||||
PINGRP_GPIO_PV1,
|
||||
PINGRP_SDMMC1_CLK,
|
||||
PINGRP_SDMMC1_CMD,
|
||||
PINGRP_SDMMC1_DAT3,
|
||||
PINGRP_SDMMC1_DAT2,
|
||||
PINGRP_SDMMC1_DAT1,
|
||||
PINGRP_SDMMC1_DAT0,
|
||||
PINGRP_GPIO_PV2,
|
||||
PINGRP_GPIO_PV3,
|
||||
PINGRP_CLK2_OUT,
|
||||
PINGRP_CLK2_REQ,
|
||||
PINGRP_LCD_PWR1,
|
||||
PINGRP_LCD_PWR2,
|
||||
PINGRP_LCD_SDIN,
|
||||
PINGRP_LCD_SDOUT,
|
||||
PINGRP_LCD_WR_N,
|
||||
PINGRP_LCD_CS0_N,
|
||||
PINGRP_LCD_DC0,
|
||||
PINGRP_LCD_SCK,
|
||||
PINGRP_LCD_PWR0,
|
||||
PINGRP_LCD_PCLK,
|
||||
PINGRP_LCD_DE,
|
||||
PINGRP_LCD_HSYNC,
|
||||
PINGRP_LCD_VSYNC,
|
||||
PINGRP_LCD_D0,
|
||||
PINGRP_LCD_D1,
|
||||
PINGRP_LCD_D2,
|
||||
PINGRP_LCD_D3,
|
||||
PINGRP_LCD_D4,
|
||||
PINGRP_LCD_D5,
|
||||
PINGRP_LCD_D6,
|
||||
PINGRP_LCD_D7,
|
||||
PINGRP_LCD_D8,
|
||||
PINGRP_LCD_D9,
|
||||
PINGRP_LCD_D10,
|
||||
PINGRP_LCD_D11,
|
||||
PINGRP_LCD_D12,
|
||||
PINGRP_LCD_D13,
|
||||
PINGRP_LCD_D14,
|
||||
PINGRP_LCD_D15,
|
||||
PINGRP_LCD_D16,
|
||||
PINGRP_LCD_D17,
|
||||
PINGRP_LCD_D18,
|
||||
PINGRP_LCD_D19,
|
||||
PINGRP_LCD_D20,
|
||||
PINGRP_LCD_D21,
|
||||
PINGRP_LCD_D22,
|
||||
PINGRP_LCD_D23,
|
||||
PINGRP_LCD_CS1_N,
|
||||
PINGRP_LCD_M1,
|
||||
PINGRP_LCD_DC1,
|
||||
PINGRP_HDMI_INT,
|
||||
PINGRP_DDC_SCL,
|
||||
PINGRP_DDC_SDA,
|
||||
PINGRP_CRT_HSYNC,
|
||||
PINGRP_CRT_VSYNC,
|
||||
PINGRP_VI_D0,
|
||||
PINGRP_VI_D1,
|
||||
PINGRP_VI_D2,
|
||||
PINGRP_VI_D3,
|
||||
PINGRP_VI_D4,
|
||||
PINGRP_VI_D5,
|
||||
PINGRP_VI_D6,
|
||||
PINGRP_VI_D7,
|
||||
PINGRP_VI_D8,
|
||||
PINGRP_VI_D9,
|
||||
PINGRP_VI_D10,
|
||||
PINGRP_VI_D11,
|
||||
PINGRP_VI_PCLK,
|
||||
PINGRP_VI_MCLK,
|
||||
PINGRP_VI_VSYNC,
|
||||
PINGRP_VI_HSYNC,
|
||||
PINGRP_UART2_RXD,
|
||||
PINGRP_UART2_TXD,
|
||||
PINGRP_UART2_RTS_N,
|
||||
PINGRP_UART2_CTS_N,
|
||||
PINGRP_UART3_TXD,
|
||||
PINGRP_UART3_RXD,
|
||||
PINGRP_UART3_CTS_N,
|
||||
PINGRP_UART3_RTS_N,
|
||||
PINGRP_GPIO_PU0,
|
||||
PINGRP_GPIO_PU1,
|
||||
PINGRP_GPIO_PU2,
|
||||
PINGRP_GPIO_PU3,
|
||||
PINGRP_GPIO_PU4,
|
||||
PINGRP_GPIO_PU5,
|
||||
PINGRP_GPIO_PU6,
|
||||
PINGRP_GEN1_I2C_SDA,
|
||||
PINGRP_GEN1_I2C_SCL,
|
||||
PINGRP_DAP4_FS,
|
||||
PINGRP_DAP4_DIN,
|
||||
PINGRP_DAP4_DOUT,
|
||||
PINGRP_DAP4_SCLK,
|
||||
PINGRP_CLK3_OUT,
|
||||
PINGRP_CLK3_REQ,
|
||||
PINGRP_GMI_WP_N,
|
||||
PINGRP_GMI_IORDY,
|
||||
PINGRP_GMI_WAIT,
|
||||
PINGRP_GMI_ADV_N,
|
||||
PINGRP_GMI_CLK,
|
||||
PINGRP_GMI_CS0_N,
|
||||
PINGRP_GMI_CS1_N,
|
||||
PINGRP_GMI_CS2_N,
|
||||
PINGRP_GMI_CS3_N,
|
||||
PINGRP_GMI_CS4_N,
|
||||
PINGRP_GMI_CS6_N,
|
||||
PINGRP_GMI_CS7_N,
|
||||
PINGRP_GMI_AD0,
|
||||
PINGRP_GMI_AD1,
|
||||
PINGRP_GMI_AD2,
|
||||
PINGRP_GMI_AD3,
|
||||
PINGRP_GMI_AD4,
|
||||
PINGRP_GMI_AD5,
|
||||
PINGRP_GMI_AD6,
|
||||
PINGRP_GMI_AD7,
|
||||
PINGRP_GMI_AD8,
|
||||
PINGRP_GMI_AD9,
|
||||
PINGRP_GMI_AD10,
|
||||
PINGRP_GMI_AD11,
|
||||
PINGRP_GMI_AD12,
|
||||
PINGRP_GMI_AD13,
|
||||
PINGRP_GMI_AD14,
|
||||
PINGRP_GMI_AD15,
|
||||
PINGRP_GMI_A16,
|
||||
PINGRP_GMI_A17,
|
||||
PINGRP_GMI_A18,
|
||||
PINGRP_GMI_A19,
|
||||
PINGRP_GMI_WR_N,
|
||||
PINGRP_GMI_OE_N,
|
||||
PINGRP_GMI_DQS,
|
||||
PINGRP_GMI_RST_N,
|
||||
PINGRP_GEN2_I2C_SCL,
|
||||
PINGRP_GEN2_I2C_SDA,
|
||||
PINGRP_SDMMC4_CLK,
|
||||
PINGRP_SDMMC4_CMD,
|
||||
PINGRP_SDMMC4_DAT0,
|
||||
PINGRP_SDMMC4_DAT1,
|
||||
PINGRP_SDMMC4_DAT2,
|
||||
PINGRP_SDMMC4_DAT3,
|
||||
PINGRP_SDMMC4_DAT4,
|
||||
PINGRP_SDMMC4_DAT5,
|
||||
PINGRP_SDMMC4_DAT6,
|
||||
PINGRP_SDMMC4_DAT7,
|
||||
PINGRP_SDMMC4_RST_N,
|
||||
PINGRP_CAM_MCLK,
|
||||
PINGRP_GPIO_PCC1,
|
||||
PINGRP_GPIO_PBB0,
|
||||
PINGRP_CAM_I2C_SCL,
|
||||
PINGRP_CAM_I2C_SDA,
|
||||
PINGRP_GPIO_PBB3,
|
||||
PINGRP_GPIO_PBB4,
|
||||
PINGRP_GPIO_PBB5,
|
||||
PINGRP_GPIO_PBB6,
|
||||
PINGRP_GPIO_PBB7,
|
||||
PINGRP_GPIO_PCC2,
|
||||
PINGRP_JTAG_RTCK,
|
||||
PINGRP_PWR_I2C_SCL,
|
||||
PINGRP_PWR_I2C_SDA,
|
||||
PINGRP_KB_ROW0,
|
||||
PINGRP_KB_ROW1,
|
||||
PINGRP_KB_ROW2,
|
||||
PINGRP_KB_ROW3,
|
||||
PINGRP_KB_ROW4,
|
||||
PINGRP_KB_ROW5,
|
||||
PINGRP_KB_ROW6,
|
||||
PINGRP_KB_ROW7,
|
||||
PINGRP_KB_ROW8,
|
||||
PINGRP_KB_ROW9,
|
||||
PINGRP_KB_ROW10,
|
||||
PINGRP_KB_ROW11,
|
||||
PINGRP_KB_ROW12,
|
||||
PINGRP_KB_ROW13,
|
||||
PINGRP_KB_ROW14,
|
||||
PINGRP_KB_ROW15,
|
||||
PINGRP_KB_COL0,
|
||||
PINGRP_KB_COL1,
|
||||
PINGRP_KB_COL2,
|
||||
PINGRP_KB_COL3,
|
||||
PINGRP_KB_COL4,
|
||||
PINGRP_KB_COL5,
|
||||
PINGRP_KB_COL6,
|
||||
PINGRP_KB_COL7,
|
||||
PINGRP_CLK_32K_OUT,
|
||||
PINGRP_SYS_CLK_REQ,
|
||||
PINGRP_CORE_PWR_REQ,
|
||||
PINGRP_CPU_PWR_REQ,
|
||||
PINGRP_PWR_INT_N,
|
||||
PINGRP_CLK_32K_IN,
|
||||
PINGRP_OWR,
|
||||
PINGRP_DAP1_FS,
|
||||
PINGRP_DAP1_DIN,
|
||||
PINGRP_DAP1_DOUT,
|
||||
PINGRP_DAP1_SCLK,
|
||||
PINGRP_CLK1_REQ,
|
||||
PINGRP_CLK1_OUT,
|
||||
PINGRP_SPDIF_IN,
|
||||
PINGRP_SPDIF_OUT,
|
||||
PINGRP_DAP2_FS,
|
||||
PINGRP_DAP2_DIN,
|
||||
PINGRP_DAP2_DOUT,
|
||||
PINGRP_DAP2_SCLK,
|
||||
PINGRP_SPI2_MOSI,
|
||||
PINGRP_SPI2_MISO,
|
||||
PINGRP_SPI2_CS0_N,
|
||||
PINGRP_SPI2_SCK,
|
||||
PINGRP_SPI1_MOSI,
|
||||
PINGRP_SPI1_SCK,
|
||||
PINGRP_SPI1_CS0_N,
|
||||
PINGRP_SPI1_MISO,
|
||||
PINGRP_SPI2_CS1_N,
|
||||
PINGRP_SPI2_CS2_N,
|
||||
PINGRP_SDMMC3_CLK,
|
||||
PINGRP_SDMMC3_CMD,
|
||||
PINGRP_SDMMC3_DAT0,
|
||||
PINGRP_SDMMC3_DAT1,
|
||||
PINGRP_SDMMC3_DAT2,
|
||||
PINGRP_SDMMC3_DAT3,
|
||||
PINGRP_SDMMC3_DAT4,
|
||||
PINGRP_SDMMC3_DAT5,
|
||||
PINGRP_SDMMC3_DAT6,
|
||||
PINGRP_SDMMC3_DAT7,
|
||||
PINGRP_PEX_L0_PRSNT_N,
|
||||
PINGRP_PEX_L0_RST_N,
|
||||
PINGRP_PEX_L0_CLKREQ_N,
|
||||
PINGRP_PEX_WAKE_N,
|
||||
PINGRP_PEX_L1_PRSNT_N,
|
||||
PINGRP_PEX_L1_RST_N,
|
||||
PINGRP_PEX_L1_CLKREQ_N,
|
||||
PINGRP_PEX_L2_PRSNT_N,
|
||||
PINGRP_PEX_L2_RST_N,
|
||||
PINGRP_PEX_L2_CLKREQ_N,
|
||||
PINGRP_HDMI_CEC, /* offset 0x33e0 */
|
||||
PINGRP_COUNT,
|
||||
};
|
||||
|
||||
enum pdrive_pingrp {
|
||||
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
|
||||
PDRIVE_PINGROUP_AO2,
|
||||
PDRIVE_PINGROUP_AT1,
|
||||
PDRIVE_PINGROUP_AT2,
|
||||
PDRIVE_PINGROUP_AT3,
|
||||
PDRIVE_PINGROUP_AT4,
|
||||
PDRIVE_PINGROUP_AT5,
|
||||
PDRIVE_PINGROUP_CDEV1,
|
||||
PDRIVE_PINGROUP_CDEV2,
|
||||
PDRIVE_PINGROUP_CSUS,
|
||||
PDRIVE_PINGROUP_DAP1,
|
||||
PDRIVE_PINGROUP_DAP2,
|
||||
PDRIVE_PINGROUP_DAP3,
|
||||
PDRIVE_PINGROUP_DAP4,
|
||||
PDRIVE_PINGROUP_DBG,
|
||||
PDRIVE_PINGROUP_LCD1,
|
||||
PDRIVE_PINGROUP_LCD2,
|
||||
PDRIVE_PINGROUP_SDIO2,
|
||||
PDRIVE_PINGROUP_SDIO3,
|
||||
PDRIVE_PINGROUP_SPI,
|
||||
PDRIVE_PINGROUP_UAA,
|
||||
PDRIVE_PINGROUP_UAB,
|
||||
PDRIVE_PINGROUP_UART2,
|
||||
PDRIVE_PINGROUP_UART3,
|
||||
PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
|
||||
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
|
||||
PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
|
||||
PDRIVE_PINGROUP_DDC,
|
||||
PDRIVE_PINGROUP_GMA,
|
||||
PDRIVE_PINGROUP_GMB,
|
||||
PDRIVE_PINGROUP_GMC,
|
||||
PDRIVE_PINGROUP_GMD,
|
||||
PDRIVE_PINGROUP_GME,
|
||||
PDRIVE_PINGROUP_GMF,
|
||||
PDRIVE_PINGROUP_GMG,
|
||||
PDRIVE_PINGROUP_GMH,
|
||||
PDRIVE_PINGROUP_OWR,
|
||||
PDRIVE_PINGROUP_UAD,
|
||||
PDRIVE_PINGROUP_GPV,
|
||||
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
|
||||
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
|
||||
PDRIVE_PINGROUP_COUNT,
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions which can be assigned to each of the pin groups. The values here
|
||||
* bear no relation to the values programmed into pinmux registers and are
|
||||
* purely a convenience. The translation is done through a table search.
|
||||
*/
|
||||
enum pmux_func {
|
||||
PMUX_FUNC_AHB_CLK,
|
||||
PMUX_FUNC_APB_CLK,
|
||||
PMUX_FUNC_AUDIO_SYNC,
|
||||
PMUX_FUNC_CRT,
|
||||
PMUX_FUNC_DAP1,
|
||||
PMUX_FUNC_DAP2,
|
||||
PMUX_FUNC_DAP3,
|
||||
PMUX_FUNC_DAP4,
|
||||
PMUX_FUNC_DAP5,
|
||||
PMUX_FUNC_DISPA,
|
||||
PMUX_FUNC_DISPB,
|
||||
PMUX_FUNC_EMC_TEST0_DLL,
|
||||
PMUX_FUNC_EMC_TEST1_DLL,
|
||||
PMUX_FUNC_GMI,
|
||||
PMUX_FUNC_GMI_INT,
|
||||
PMUX_FUNC_HDMI,
|
||||
PMUX_FUNC_I2C1,
|
||||
PMUX_FUNC_I2C2,
|
||||
PMUX_FUNC_I2C3,
|
||||
PMUX_FUNC_IDE,
|
||||
PMUX_FUNC_KBC,
|
||||
PMUX_FUNC_MIO,
|
||||
PMUX_FUNC_MIPI_HS,
|
||||
PMUX_FUNC_NAND,
|
||||
PMUX_FUNC_OSC,
|
||||
PMUX_FUNC_OWR,
|
||||
PMUX_FUNC_PCIE,
|
||||
PMUX_FUNC_PLLA_OUT,
|
||||
PMUX_FUNC_PLLC_OUT1,
|
||||
PMUX_FUNC_PLLM_OUT1,
|
||||
PMUX_FUNC_PLLP_OUT2,
|
||||
PMUX_FUNC_PLLP_OUT3,
|
||||
PMUX_FUNC_PLLP_OUT4,
|
||||
PMUX_FUNC_PWM,
|
||||
PMUX_FUNC_PWR_INTR,
|
||||
PMUX_FUNC_PWR_ON,
|
||||
PMUX_FUNC_RTCK,
|
||||
PMUX_FUNC_SDMMC1,
|
||||
PMUX_FUNC_SDMMC2,
|
||||
PMUX_FUNC_SDMMC3,
|
||||
PMUX_FUNC_SDMMC4,
|
||||
PMUX_FUNC_SFLASH,
|
||||
PMUX_FUNC_SPDIF,
|
||||
PMUX_FUNC_SPI1,
|
||||
PMUX_FUNC_SPI2,
|
||||
PMUX_FUNC_SPI2_ALT,
|
||||
PMUX_FUNC_SPI3,
|
||||
PMUX_FUNC_SPI4,
|
||||
PMUX_FUNC_TRACE,
|
||||
PMUX_FUNC_TWC,
|
||||
PMUX_FUNC_UARTA,
|
||||
PMUX_FUNC_UARTB,
|
||||
PMUX_FUNC_UARTC,
|
||||
PMUX_FUNC_UARTD,
|
||||
PMUX_FUNC_UARTE,
|
||||
PMUX_FUNC_ULPI,
|
||||
PMUX_FUNC_VI,
|
||||
PMUX_FUNC_VI_SENSOR_CLK,
|
||||
PMUX_FUNC_XIO,
|
||||
PMUX_FUNC_BLINK,
|
||||
PMUX_FUNC_CEC,
|
||||
PMUX_FUNC_CLK12,
|
||||
PMUX_FUNC_DAP,
|
||||
PMUX_FUNC_DAPSDMMC2,
|
||||
PMUX_FUNC_DDR,
|
||||
PMUX_FUNC_DEV3,
|
||||
PMUX_FUNC_DTV,
|
||||
PMUX_FUNC_VI_ALT1,
|
||||
PMUX_FUNC_VI_ALT2,
|
||||
PMUX_FUNC_VI_ALT3,
|
||||
PMUX_FUNC_EMC_DLL,
|
||||
PMUX_FUNC_EXTPERIPH1,
|
||||
PMUX_FUNC_EXTPERIPH2,
|
||||
PMUX_FUNC_EXTPERIPH3,
|
||||
PMUX_FUNC_GMI_ALT,
|
||||
PMUX_FUNC_HDA,
|
||||
PMUX_FUNC_HSI,
|
||||
PMUX_FUNC_I2C4,
|
||||
PMUX_FUNC_I2C5,
|
||||
PMUX_FUNC_I2CPWR,
|
||||
PMUX_FUNC_I2S0,
|
||||
PMUX_FUNC_I2S1,
|
||||
PMUX_FUNC_I2S2,
|
||||
PMUX_FUNC_I2S3,
|
||||
PMUX_FUNC_I2S4,
|
||||
PMUX_FUNC_NAND_ALT,
|
||||
PMUX_FUNC_POPSDIO4,
|
||||
PMUX_FUNC_POPSDMMC4,
|
||||
PMUX_FUNC_PWM0,
|
||||
PMUX_FUNC_PWM1,
|
||||
PMUX_FUNC_PWM2,
|
||||
PMUX_FUNC_PWM3,
|
||||
PMUX_FUNC_SATA,
|
||||
PMUX_FUNC_SPI5,
|
||||
PMUX_FUNC_SPI6,
|
||||
PMUX_FUNC_SYSCLK,
|
||||
PMUX_FUNC_VGP1,
|
||||
PMUX_FUNC_VGP2,
|
||||
PMUX_FUNC_VGP3,
|
||||
PMUX_FUNC_VGP4,
|
||||
PMUX_FUNC_VGP5,
|
||||
PMUX_FUNC_VGP6,
|
||||
PMUX_FUNC_CLK_12M_OUT,
|
||||
PMUX_FUNC_HDCP,
|
||||
PMUX_FUNC_TEST,
|
||||
PMUX_FUNC_CORE_PWR_REQ,
|
||||
PMUX_FUNC_CPU_PWR_REQ,
|
||||
PMUX_FUNC_PWR_INT_N,
|
||||
PMUX_FUNC_CLK_32K_IN,
|
||||
PMUX_FUNC_SAFE,
|
||||
|
||||
PMUX_FUNC_MAX,
|
||||
|
||||
PMUX_FUNC_RSVD1 = 0x8000,
|
||||
PMUX_FUNC_RSVD2 = 0x8001,
|
||||
PMUX_FUNC_RSVD3 = 0x8002,
|
||||
PMUX_FUNC_RSVD4 = 0x8003,
|
||||
};
|
||||
|
||||
/* return 1 if a pmux_func is in range */
|
||||
#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
|
||||
|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
|
||||
|
||||
/* return 1 if a pingrp is in range */
|
||||
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
|
||||
|
||||
/* The pullup/pulldown state of a pin group */
|
||||
enum pmux_pull {
|
||||
PMUX_PULL_NORMAL = 0,
|
||||
PMUX_PULL_DOWN,
|
||||
PMUX_PULL_UP,
|
||||
};
|
||||
/* return 1 if a pin_pupd_is in range */
|
||||
#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
|
||||
((pupd) <= PMUX_PULL_UP))
|
||||
|
||||
/* Defines whether a pin group is tristated or in normal operation */
|
||||
enum pmux_tristate {
|
||||
PMUX_TRI_NORMAL = 0,
|
||||
PMUX_TRI_TRISTATE = 1,
|
||||
};
|
||||
/* return 1 if a pin_tristate_is in range */
|
||||
#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
|
||||
&& ((tristate) <= PMUX_TRI_TRISTATE))
|
||||
|
||||
enum pmux_pin_io {
|
||||
PMUX_PIN_OUTPUT = 0,
|
||||
PMUX_PIN_INPUT = 1,
|
||||
};
|
||||
/* return 1 if a pin_io_is in range */
|
||||
#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
|
||||
((io) <= PMUX_PIN_INPUT))
|
||||
|
||||
enum pmux_pin_lock {
|
||||
PMUX_PIN_LOCK_DEFAULT = 0,
|
||||
PMUX_PIN_LOCK_DISABLE,
|
||||
PMUX_PIN_LOCK_ENABLE,
|
||||
};
|
||||
/* return 1 if a pin_lock is in range */
|
||||
#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
|
||||
((lock) <= PMUX_PIN_LOCK_ENABLE))
|
||||
|
||||
enum pmux_pin_od {
|
||||
PMUX_PIN_OD_DEFAULT = 0,
|
||||
PMUX_PIN_OD_DISABLE,
|
||||
PMUX_PIN_OD_ENABLE,
|
||||
};
|
||||
/* return 1 if a pin_od is in range */
|
||||
#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
|
||||
((od) <= PMUX_PIN_OD_ENABLE))
|
||||
|
||||
enum pmux_pin_ioreset {
|
||||
PMUX_PIN_IO_RESET_DEFAULT = 0,
|
||||
PMUX_PIN_IO_RESET_DISABLE,
|
||||
PMUX_PIN_IO_RESET_ENABLE,
|
||||
};
|
||||
/* return 1 if a pin_ioreset_is in range */
|
||||
#define pmux_pin_ioreset_isvalid(ioreset) \
|
||||
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
|
||||
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
|
||||
|
||||
/* Available power domains used by pin groups */
|
||||
enum pmux_vddio {
|
||||
PMUX_VDDIO_BB = 0,
|
||||
PMUX_VDDIO_LCD,
|
||||
PMUX_VDDIO_VI,
|
||||
PMUX_VDDIO_UART,
|
||||
PMUX_VDDIO_DDR,
|
||||
PMUX_VDDIO_NAND,
|
||||
PMUX_VDDIO_SYS,
|
||||
PMUX_VDDIO_AUDIO,
|
||||
PMUX_VDDIO_SD,
|
||||
PMUX_VDDIO_CAM,
|
||||
PMUX_VDDIO_GMI,
|
||||
PMUX_VDDIO_PEXCTL,
|
||||
PMUX_VDDIO_SDMMC1,
|
||||
PMUX_VDDIO_SDMMC3,
|
||||
PMUX_VDDIO_SDMMC4,
|
||||
|
||||
PMUX_VDDIO_NONE
|
||||
};
|
||||
|
||||
/* t30 pin drive group and pin mux registers */
|
||||
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
|
||||
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
|
||||
PDRIVE_PINGROUP_COUNT)
|
||||
struct pmux_tri_ctlr {
|
||||
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
|
||||
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
|
||||
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
|
||||
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
|
||||
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
|
||||
uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
|
||||
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
|
||||
|
||||
uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
|
||||
|
||||
uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
|
||||
uint pmt_reserved5[PMUX_OFFSET];
|
||||
uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
|
||||
};
|
||||
|
||||
/*
|
||||
* This defines the configuration for a pin, including the function assigned,
|
||||
* pull up/down settings and tristate settings. Having set up one of these
|
||||
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
|
||||
* available is pinmux_config_table() to configure a list of pins.
|
||||
*/
|
||||
struct pingroup_config {
|
||||
enum pmux_pingrp pingroup; /* pin group PINGRP_... */
|
||||
enum pmux_func func; /* function to assign FUNC_... */
|
||||
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
|
||||
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
|
||||
enum pmux_pin_io io; /* input or output PMUX_PIN_... */
|
||||
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
|
||||
enum pmux_pin_od od; /* open-drain or push-pull driver */
|
||||
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
|
||||
};
|
||||
|
||||
/* Set a pin group to tristate */
|
||||
void pinmux_tristate_enable(enum pmux_pingrp pin);
|
||||
|
||||
/* Set a pin group to normal (non tristate) */
|
||||
void pinmux_tristate_disable(enum pmux_pingrp pin);
|
||||
|
||||
/* Set the pull up/down feature for a pin group */
|
||||
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
|
||||
|
||||
/* Set the mux function for a pin group */
|
||||
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
|
||||
|
||||
/* Set the complete configuration for a pin group */
|
||||
void pinmux_config_pingroup(struct pingroup_config *config);
|
||||
|
||||
/* Set a pin group to tristate or normal */
|
||||
void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
|
||||
|
||||
/* Set a pin group as input or output */
|
||||
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
|
||||
|
||||
/**
|
||||
* Configure a list of pin groups
|
||||
*
|
||||
* @param config List of config items
|
||||
* @param len Number of config items in list
|
||||
*/
|
||||
void pinmux_config_table(struct pingroup_config *config, int len);
|
||||
|
||||
/* Set a group of pins from a table */
|
||||
void pinmux_init(void);
|
||||
|
||||
#endif /* _TEGRA30_PINMUX_H_ */
|
23
arch/arm/include/asm/arch-tegra30/pmu.h
Normal file
23
arch/arm/include/asm/arch-tegra30/pmu.h
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_PMU_H_
|
||||
#define _TEGRA30_PMU_H_
|
||||
|
||||
/* Set core and CPU voltages to nominal levels */
|
||||
int pmu_set_nominal(void);
|
||||
|
||||
#endif /* _TEGRA30_PMU_H_ */
|
28
arch/arm/include/asm/arch-tegra30/spl.h
Normal file
28
arch/arm/include/asm/arch-tegra30/spl.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
#define BOOT_DEVICE_RAM 1
|
||||
|
||||
#endif
|
28
arch/arm/include/asm/arch-tegra30/tegra.h
Normal file
28
arch/arm/include/asm/arch-tegra30/tegra.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_H_
|
||||
#define _TEGRA30_H_
|
||||
|
||||
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
|
||||
|
||||
#include <asm/arch-tegra/tegra.h>
|
||||
|
||||
#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
|
||||
|
||||
#define MAX_NUM_CPU 4
|
||||
|
||||
#endif /* TEGRA30_H */
|
85
arch/arm/include/asm/arch-zynq/hardware.h
Normal file
85
arch/arm/include/asm/arch-zynq/hardware.h
Normal file
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2013 Xilinx Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_HARDWARE_H
|
||||
#define _ASM_ARCH_HARDWARE_H
|
||||
|
||||
#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
|
||||
#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
|
||||
#define XPSS_SCU_BASEADDR 0xF8F00000
|
||||
|
||||
/* Reflect slcr offsets */
|
||||
struct slcr_regs {
|
||||
u32 scl; /* 0x0 */
|
||||
u32 slcr_lock; /* 0x4 */
|
||||
u32 slcr_unlock; /* 0x8 */
|
||||
u32 reserved1[125];
|
||||
u32 pss_rst_ctrl; /* 0x200 */
|
||||
u32 reserved2[15];
|
||||
u32 fpga_rst_ctrl; /* 0x240 */
|
||||
u32 reserved3[5];
|
||||
u32 reboot_status; /* 0x258 */
|
||||
u32 boot_mode; /* 0x25c */
|
||||
u32 reserved4[116];
|
||||
u32 trust_zone; /* 0x430 */ /* FIXME */
|
||||
u32 reserved5[115];
|
||||
u32 ddr_urgent; /* 0x600 */
|
||||
u32 reserved6[6];
|
||||
u32 ddr_urgent_sel; /* 0x61c */
|
||||
u32 reserved7[188];
|
||||
u32 ocm_cfg; /* 0x910 */
|
||||
};
|
||||
|
||||
#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
|
||||
|
||||
struct devcfg_regs {
|
||||
u32 ctrl; /* 0x0 */
|
||||
u32 lock; /* 0x4 */
|
||||
u32 cfg; /* 0x8 */
|
||||
u32 int_sts; /* 0xc */
|
||||
u32 int_mask; /* 0x10 */
|
||||
u32 status; /* 0x14 */
|
||||
u32 dma_src_addr; /* 0x18 */
|
||||
u32 dma_dst_addr; /* 0x1c */
|
||||
u32 dma_src_len; /* 0x20 */
|
||||
u32 dma_dst_len; /* 0x24 */
|
||||
u32 rom_shadow; /* 0x28 */
|
||||
u32 reserved1[2];
|
||||
u32 unlock; /* 0x34 */
|
||||
u32 reserved2[18];
|
||||
u32 mctrl; /* 0x80 */
|
||||
u32 reserved3;
|
||||
u32 write_count; /* 0x88 */
|
||||
u32 read_count; /* 0x8c */
|
||||
};
|
||||
|
||||
#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
|
||||
|
||||
struct scu_regs {
|
||||
u32 reserved1[16];
|
||||
u32 filter_start; /* 0x40 */
|
||||
u32 filter_end; /* 0x44 */
|
||||
};
|
||||
|
||||
#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
|
||||
|
||||
#endif /* _ASM_ARCH_HARDWARE_H */
|
30
arch/arm/include/asm/arch-zynq/sys_proto.h
Normal file
30
arch/arm/include/asm/arch-zynq/sys_proto.h
Normal file
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* Copyright (c) 2013 Xilinx Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
|
||||
extern void zynq_slcr_lock(void);
|
||||
extern void zynq_slcr_unlock(void);
|
||||
extern void zynq_slcr_cpu_reset(void);
|
||||
|
||||
#endif /* _SYS_PROTO_H_ */
|
@@ -23,27 +23,11 @@
|
||||
|
||||
#ifndef __ASM_GBL_DATA_H
|
||||
#define __ASM_GBL_DATA_H
|
||||
/*
|
||||
* The following data structure is placed in some memory which is
|
||||
* available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
|
||||
* some locked parts of the data cache) to allow for a minimum set of
|
||||
* global variables during system initialization (until we have set
|
||||
* up the memory controller so that we can use RAM).
|
||||
*/
|
||||
|
||||
typedef struct global_data {
|
||||
bd_t *bd;
|
||||
unsigned long flags;
|
||||
unsigned int baudrate;
|
||||
unsigned long have_console; /* serial_init() was called */
|
||||
#ifdef CONFIG_PRE_CONSOLE_BUFFER
|
||||
unsigned long precon_buf_idx; /* Pre-Console buffer index */
|
||||
#endif
|
||||
unsigned long env_addr; /* Address of Environment struct */
|
||||
unsigned long env_valid; /* Checksum of Environment valid? */
|
||||
unsigned long fb_base; /* base address of frame buffer */
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
unsigned long sdhc_clk;
|
||||
/* Architecture-specific global data */
|
||||
struct arch_global_data {
|
||||
#if defined(CONFIG_FSL_ESDHC)
|
||||
u32 sdhc_clk;
|
||||
#endif
|
||||
#ifdef CONFIG_AT91FAMILY
|
||||
/* "static data" needed by at91's clock.c */
|
||||
@@ -54,38 +38,22 @@ typedef struct global_data {
|
||||
unsigned long pllb_rate_hz;
|
||||
unsigned long at91_pllb_usb_init;
|
||||
#endif
|
||||
#ifdef CONFIG_ARM
|
||||
/* "static data" needed by most of timer.c on ARM platforms */
|
||||
unsigned long timer_rate_hz;
|
||||
unsigned long tbl;
|
||||
unsigned long tbu;
|
||||
unsigned long long timer_reset_value;
|
||||
unsigned long lastinc;
|
||||
#endif
|
||||
unsigned long timer_rate_hz;
|
||||
unsigned long tbu;
|
||||
unsigned long tbl;
|
||||
unsigned long lastinc;
|
||||
unsigned long long timer_reset_value;
|
||||
#ifdef CONFIG_IXP425
|
||||
unsigned long timestamp;
|
||||
unsigned long timestamp;
|
||||
#endif
|
||||
unsigned long relocaddr; /* Start address of U-Boot in RAM */
|
||||
phys_size_t ram_size; /* RAM size */
|
||||
unsigned long mon_len; /* monitor len */
|
||||
unsigned long irq_sp; /* irq stack pointer */
|
||||
unsigned long start_addr_sp; /* start_addr_stackpointer */
|
||||
unsigned long reloc_off;
|
||||
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
|
||||
unsigned long tlb_addr;
|
||||
unsigned long tlb_size;
|
||||
unsigned long tlb_addr;
|
||||
unsigned long tlb_size;
|
||||
#endif
|
||||
const void *fdt_blob; /* Our device tree, NULL if none */
|
||||
void **jt; /* jump table */
|
||||
char env_buf[32]; /* buffer for getenv() before reloc. */
|
||||
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
|
||||
unsigned long post_log_word; /* Record POST activities */
|
||||
unsigned long post_log_res; /* success of POST test */
|
||||
unsigned long post_init_f_time; /* When post_init_f started */
|
||||
#endif
|
||||
} gd_t;
|
||||
};
|
||||
|
||||
#include <asm-generic/global_data_flags.h>
|
||||
#include <asm-generic/global_data.h>
|
||||
|
||||
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
|
||||
|
||||
|
@@ -61,6 +61,12 @@
|
||||
|
||||
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
|
||||
|
||||
#ifdef __ARM_ARCH_7A__
|
||||
#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
|
||||
#else
|
||||
#define wfi()
|
||||
#endif
|
||||
|
||||
static inline unsigned int get_cr(void)
|
||||
{
|
||||
unsigned int val;
|
||||
|
Reference in New Issue
Block a user