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Merge tag 'u-boot-rockchip-20220418' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

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- Add rk3066 SoC support;
- Add rk3066 MK808 board support;
- dts sync from kernel for rk322x, rk3288;
- some other board level config update;
This commit is contained in:
Tom Rini
2022-04-19 08:50:23 -04:00
parent aec75a3d1d dcaaefdc0a
commit 9acf3726b6
123 changed files with 5573 additions and 599 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/Makefile
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@@ -90,6 +90,9 @@ dtb-$(CONFIG_ROCKCHIP_PX30) += \
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
dtb-$(CONFIG_ROCKCHIP_RK3066) += \
rk3066a-mk808.dtb
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
rk3128-evb.dtb

49
arch/arm/dts/rk3066a-mk808-u-boot.dtsi Normal file
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@@ -0,0 +1,49 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk3066a-u-boot.dtsi"
/ {
config {
u-boot,boot-led = "mk808:blue:power";
};
};
&cru {
u-boot,dm-pre-reloc;
};
&dmc {
compatible = "rockchip,rk3066-dmc", "syscon";
rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4
0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0
0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0
0x4 0x0>;
rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
0x220 0x40 0x0 0x0>;
rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>;
};
&mmc0 {
fifo-mode;
max-frequency = <4000000>;
u-boot,dm-spl;
u-boot,spl-fifo-mode;
};
&mmc1 {
status = "disabled";
};
&noc {
compatible = "rockchip,rk3066-noc", "syscon";
};
&timer2 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};

216
arch/arm/dts/rk3066a-mk808.dts Normal file
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@@ -0,0 +1,216 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2016 Paweł Jarosz <paweljarosz3691@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3066a.dtsi"
/ {
model = "Rikomagic MK808";
compatible = "rikomagic,mk808", "rockchip,rk3066a";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
};
chosen {
stdout-path = "serial2:115200n8";
};
memory@60000000 {
reg = <0x60000000 0x40000000>;
device_type = "memory";
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <2500000>;
poll-interval = <100>;
recovery {
label = "recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <0>;
};
};
gpio-leds {
compatible = "gpio-leds";
blue_led: led-0 {
label = "mk808:blue:power";
gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "default-on";
};
};
hdmi_con {
compatible = "hdmi-connector";
type = "c";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
vcc_2v5: vcc-2v5 {
compatible = "regulator-fixed";
regulator-name = "vcc_2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_host: usb-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&host_drv>;
pinctrl-names = "default";
regulator-always-on;
regulator-name = "host-pwr";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
vcc_otg: usb-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&otg_drv>;
pinctrl-names = "default";
regulator-always-on;
regulator-name = "vcc_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sdmmc_pwr>;
pinctrl-names = "default";
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
vcc_wifi: sdio-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&wifi_pwr>;
pinctrl-names = "default";
regulator-name = "vcc_wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
};
&hdmi {
status = "okay";
};
&hdmi_in_vop1 {
status = "disabled";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mmc0 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
vmmc-supply = <&vcc_sd>;
status = "okay";
};
&mmc1 {
bus-width = <4>;
non-removable;
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
pinctrl-names = "default";
vmmc-supply = <&vcc_wifi>;
status = "okay";
};
&pinctrl {
usb-host {
host_drv: host-drv {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_default>;
};
};
usb-otg {
otg_drv: otg-drv {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_default>;
};
};
sdmmc {
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_default>;
};
};
sdio {
wifi_pwr: wifi-pwr {
rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&saradc {
vref-supply = <&vcc_2v5>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host {
status = "okay";
};
&usb_otg {
status = "okay";
};
&usbphy {
status = "okay";
};
&vop0 {
status = "okay";
};
&wdt {
status = "okay";
};

4
arch/arm/dts/rk3066a-u-boot.dtsi Normal file
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@@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rockchip-u-boot.dtsi"
#include "rk3xxx-u-boot.dtsi"

879
arch/arm/dts/rk3066a.dtsi Normal file
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@@ -0,0 +1,879 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include <dt-bindings/power/rk3066-power.h>
#include "rk3xxx.dtsi"
/ {
compatible = "rockchip,rk3066a";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "rockchip,rk3066-smp";
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
operating-points =
/* kHz uV */
<1416000 1300000>,
<1200000 1175000>,
<1008000 1125000>,
<816000 1125000>,
<600000 1100000>,
<504000 1100000>,
<312000 1075000>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x1>;
};
};
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop0_out>, <&vop1_out>;
};
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x10000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x0 0x50>;
};
};
vop0: vop@1010c000 {
compatible = "rockchip,rk3066-vop";
reg = <0x1010c000 0x19c>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC0>,
<&cru DCLK_LCDC0>,
<&cru HCLK_LCDC0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3066_PD_VIO>;
resets = <&cru SRST_LCDC0_AXI>,
<&cru SRST_LCDC0_AHB>,
<&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vop0_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop0_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop0>;
};
};
};
vop1: vop@1010e000 {
compatible = "rockchip,rk3066-vop";
reg = <0x1010e000 0x19c>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC1>,
<&cru DCLK_LCDC1>,
<&cru HCLK_LCDC1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3066_PD_VIO>;
resets = <&cru SRST_LCDC1_AXI>,
<&cru SRST_LCDC1_AHB>,
<&cru SRST_LCDC1_DCLK>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vop1_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop1_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop1>;
};
};
};
hdmi: hdmi@10116000 {
compatible = "rockchip,rk3066-hdmi";
reg = <0x10116000 0x2000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HDMI>;
clock-names = "hclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
power-domains = <&power RK3066_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vop0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop0_out_hdmi>;
};
hdmi_in_vop1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vop1_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
};
};
};
i2s0: i2s@10118000 {
compatible = "rockchip,rk3066-i2s";
reg = <0x10118000 0x2000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac1_s 4>, <&dmac1_s 5>;
dma-names = "tx", "rx";
rockchip,playback-channels = <8>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s1: i2s@1011a000 {
compatible = "rockchip,rk3066-i2s";
reg = <0x1011a000 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac1_s 6>, <&dmac1_s 7>;
dma-names = "tx", "rx";
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s2: i2s@1011c000 {
compatible = "rockchip,rk3066-i2s";
reg = <0x1011c000 0x2000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac1_s 9>, <&dmac1_s 10>;
dma-names = "tx", "rx";
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "disabled";
};
cru: clock-controller@20000000 {
compatible = "rockchip,rk3066a-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
<&cru ACLK_CPU>, <&cru HCLK_CPU>,
<&cru PCLK_CPU>, <&cru ACLK_PERI>,
<&cru HCLK_PERI>, <&cru PCLK_PERI>;
assigned-clock-rates = <400000000>, <594000000>,
<300000000>, <150000000>,
<75000000>, <300000000>,
<150000000>, <75000000>;
};
timer2: timer@2000e000 {
compatible = "snps,dw-apb-timer";
reg = <0x2000e000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
clock-names = "timer", "pclk";
};
efuse: efuse@20010000 {
compatible = "rockchip,rk3066a-efuse";
reg = <0x20010000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE>;
clock-names = "pclk_efuse";
cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
};
timer0: timer@20038000 {
compatible = "snps,dw-apb-timer";
reg = <0x20038000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
clock-names = "timer", "pclk";
};
timer1: timer@2003a000 {
compatible = "snps,dw-apb-timer";
reg = <0x2003a000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
clock-names = "timer", "pclk";
};
tsadc: tsadc@20060000 {
compatible = "rockchip,rk3066-tsadc";
reg = <0x20060000 0x100>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
resets = <&cru SRST_TSADC>;
reset-names = "saradc-apb";
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio@20034000 {
compatible = "rockchip,gpio-bank";
reg = <0x20034000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2003e000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003e000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@2000a000 {
compatible = "rockchip,gpio-bank";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO6>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_default: pcfg-pull-default {
bias-pull-pin-default;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
emac {
emac_xfer: emac-xfer {
rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
<1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
<1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
<1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
<1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
<1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
<1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
<1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
};
emac_mdio: emac-mdio {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
<1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
};
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
};
emmc_rst: emmc-rst {
rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
};
/*
* The data pins are shared between nandc and emmc and
* not accessible through pinctrl. Also they should've
* been already set correctly by firmware, as
* flash/emmc is the boot-device.
*/
};
hdmi {
hdmi_hpd: hdmi-hpd {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
};
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
<0 RK_PA2 1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
<2 RK_PD5 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
<2 RK_PD7 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
<3 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
<3 RK_PA3 2 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
<3 RK_PA5 1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_out: pwm0-out {
rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_out: pwm1-out {
rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_out: pwm2-out {
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_out: pwm3-out {
rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
};
spi0_tx: spi0-tx {
rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
};
spi0_rx: spi0-rx {
rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
};
};
spi1 {
spi1_clk: spi1-clk {
rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
};
spi1_rx: spi1-rx {
rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
};
spi1_tx: spi1-tx {
rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
};
spi1_cs1: spi1-cs1 {
rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
<1 RK_PA1 1 &pcfg_pull_default>;
};
uart0_cts: uart0-cts {
rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
};
uart0_rts: uart0-rts {
rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
<1 RK_PA5 1 &pcfg_pull_default>;
};
uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
};
uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
<1 RK_PB1 1 &pcfg_pull_default>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
<3 RK_PD4 1 &pcfg_pull_default>;
};
uart3_cts: uart3-cts {
rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
};
uart3_rts: uart3-rts {
rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
};
};
sd0 {
sd0_clk: sd0-clk {
rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
};
sd0_cmd: sd0-cmd {
rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
};
sd0_cd: sd0-cd {
rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
};
sd0_wp: sd0-wp {
rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
};
sd0_bus1: sd0-bus-width1 {
rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
};
sd0_bus4: sd0-bus-width4 {
rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
<3 RK_PB3 1 &pcfg_pull_default>,
<3 RK_PB4 1 &pcfg_pull_default>,
<3 RK_PB5 1 &pcfg_pull_default>;
};
};
sd1 {
sd1_clk: sd1-clk {
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
};
sd1_cmd: sd1-cmd {
rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
};
sd1_cd: sd1-cd {
rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
};
sd1_wp: sd1-wp {
rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
};
sd1_bus1: sd1-bus-width1 {
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
};
sd1_bus4: sd1-bus-width4 {
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
<3 RK_PC2 1 &pcfg_pull_default>,
<3 RK_PC3 1 &pcfg_pull_default>,
<3 RK_PC4 1 &pcfg_pull_default>;
};
};
i2s0 {
i2s0_bus: i2s0-bus {
rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
<0 RK_PB0 1 &pcfg_pull_default>,
<0 RK_PB1 1 &pcfg_pull_default>,
<0 RK_PB2 1 &pcfg_pull_default>,
<0 RK_PB3 1 &pcfg_pull_default>,
<0 RK_PB4 1 &pcfg_pull_default>,
<0 RK_PB5 1 &pcfg_pull_default>,
<0 RK_PB6 1 &pcfg_pull_default>,
<0 RK_PB7 1 &pcfg_pull_default>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
<0 RK_PC1 1 &pcfg_pull_default>,
<0 RK_PC2 1 &pcfg_pull_default>,
<0 RK_PC3 1 &pcfg_pull_default>,
<0 RK_PC4 1 &pcfg_pull_default>,
<0 RK_PC5 1 &pcfg_pull_default>;
};
};
i2s2 {
i2s2_bus: i2s2-bus {
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
<0 RK_PD1 1 &pcfg_pull_default>,
<0 RK_PD2 1 &pcfg_pull_default>,
<0 RK_PD3 1 &pcfg_pull_default>,
<0 RK_PD4 1 &pcfg_pull_default>,
<0 RK_PD5 1 &pcfg_pull_default>;
};
};
};
};
&gpu {
compatible = "rockchip,rk3066-mali", "arm,mali-400";
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pp2",
"ppmmu2",
"pp3",
"ppmmu3";
power-domains = <&power RK3066_PD_GPU>;
};
&grf {
compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
usbphy: usbphy {
compatible = "rockchip,rk3066a-usb-phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
usbphy0: usb-phy@17c {
reg = <0x17c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
#clock-cells = <0>;
#phy-cells = <0>;
};
usbphy1: usb-phy@188 {
reg = <0x188>;
clocks = <&cru SCLK_OTGPHY1>;
clock-names = "phyclk";
#clock-cells = <0>;
#phy-cells = <0>;
};
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
};
&mmc0 {
clock-frequency = <50000000>;
dmas = <&dmac2 1>;
dma-names = "rx-tx";
max-frequency = <50000000>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};
&mmc1 {
dmas = <&dmac2 3>;
dma-names = "rx-tx";
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};
&emmc {
dmas = <&dmac2 4>;
dma-names = "rx-tx";
};
&pmu {
power: power-controller {
compatible = "rockchip,rk3066-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RK3066_PD_VIO {
reg = <RK3066_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
<&cru DCLK_LCDC0>,
<&cru DCLK_LCDC1>,
<&cru HCLK_LCDC0>,
<&cru HCLK_LCDC1>,
<&cru SCLK_CIF1>,
<&cru ACLK_CIF1>,
<&cru HCLK_CIF1>,
<&cru SCLK_CIF0>,
<&cru ACLK_CIF0>,
<&cru HCLK_CIF0>,
<&cru HCLK_HDMI>,
<&cru ACLK_IPP>,
<&cru HCLK_IPP>,
<&cru ACLK_RGA>,
<&cru HCLK_RGA>;
pm_qos = <&qos_lcdc0>,
<&qos_lcdc1>,
<&qos_cif0>,
<&qos_cif1>,
<&qos_ipp>,
<&qos_rga>;
#power-domain-cells = <0>;
};
power-domain@RK3066_PD_VIDEO {
reg = <RK3066_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
#power-domain-cells = <0>;
};
power-domain@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_out>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1_out>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pwm2_out>;
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pwm3_out>;
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};
&uart0 {
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
dmas = <&dmac1_s 0>, <&dmac1_s 1>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
};
&uart1 {
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
dmas = <&dmac1_s 2>, <&dmac1_s 3>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
};
&uart2 {
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
dmas = <&dmac2 6>, <&dmac2 7>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
&uart3 {
compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
dmas = <&dmac2 8>, <&dmac2 9>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
};
&vpu {
power-domains = <&power RK3066_PD_VIDEO>;
};
&wdt {
compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};
&emac {
compatible = "rockchip,rk3066-emac";
};

1
arch/arm/dts/rk3188-u-boot.dtsi
View File

@@ -4,6 +4,7 @@
*/
#include "rockchip-u-boot.dtsi"
#include "rk3xxx-u-boot.dtsi"
&global_timer {
status = "okay";

1
arch/arm/dts/rk3188.dtsi
View File

@@ -9,7 +9,6 @@
#include <dt-bindings/clock/rk3188-cru.h>
#include <dt-bindings/power/rk3188-power.h>
#include "rk3xxx.dtsi"
#include "rk3xxx-u-boot.dtsi"
/ {
compatible = "rockchip,rk3188";

28
arch/arm/dts/rk3229-evb-u-boot.dtsi Normal file
View File

@@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include "rk322x-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
};
&dmc {
rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
0x0 0x924>;
rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
0 300 3 0 120>;
};
&emmc {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};

221
arch/arm/dts/rk3229-evb.dts
View File

@@ -1,18 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
*/
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk322x.dtsi"
#include <dt-bindings/input/input.h>
#include "rk3229.dtsi"
/ {
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
chosen {
stdout-path = &uart2;
aliases {
mmc0 = &emmc;
};
memory@60000000 {
@@ -20,6 +18,15 @@
reg = <0x60000000 0x40000000>;
};
dc_12v: dc-12v-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
ext_gmac: ext_gmac {
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -27,6 +34,18 @@
#clock-cells = <0>;
};
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -35,18 +54,95 @@
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vccio_1v8>;
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vccio_1v8: vccio-1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "vccio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vccio_3v3: vccio-3v3-regulator {
compatible = "regulator-fixed";
regulator-name = "vccio_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vdd_arm: vdd-arm-regulator {
compatible = "pwm-regulator";
pwms = <&pwm1 0 25000 1>;
pwm-supply = <&vcc_sys>;
regulator-name = "vdd_arm";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
};
vdd_log: vdd-log-regulator {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
pwm-supply = <&vcc_sys>;
regulator-name = "vdd_log";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
gpio_keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power_key: power-key {
label = "GPIO Key Power";
gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <100>;
wakeup-source;
};
};
};
&dmc {
rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
0x0 0x924>;
rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
0 300 3 0 120>;
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
cap-mmc-highspeed;
non-removable;
status = "okay";
};
&gmac {
@@ -65,27 +161,96 @@
status = "okay";
};
&emmc {
u-boot,dm-pre-reloc;
&io_domains {
status = "okay";
vccio1-supply = <&vccio_3v3>;
vccio2-supply = <&vccio_1v8>;
vccio4-supply = <&vccio_3v3>;
};
&pinctrl {
keys {
pwr_key: pwr-key {
rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {
status = "okay";
};
&sdmmc {
&pwm2 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
status = "okay";
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
num-slots = <1>;
supports-sd;
};
&uart2 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb20_otg {
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
phy-supply = <&vcc_host>;
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc_host>;
status = "okay";
};
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host2_ehci {
status = "okay";
};
&usb_host2_ohci {
status = "okay";
};
&usb_otg {
status = "okay";
};

52
arch/arm/dts/rk3229.dtsi Normal file
View File

@@ -0,0 +1,52 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
*/
#include "rk322x.dtsi"
/ {
compatible = "rockchip,rk3229";
/delete-node/ opp-table0;
cpu0_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <975000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1175000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1275000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1325000>;
};
opp-1392000000 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <1375000>;
};
opp-1464000000 {
opp-hz = /bits/ 64 <1464000000>;
opp-microvolt = <1400000>;
};
};
};

56
arch/arm/dts/rk322x-u-boot.dtsi Normal file
View File

@@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rockchip-u-boot.dtsi"
/ {
bus_intmem@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x9000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x9000>;
smp-sram@0 {
compatible = "rockchip,rk322x-smp-sram";
reg = <0x00 0x10>;
};
ddr_sram: ddr-sram@1000 {
compatible = "rockchip,rk322x-ddr-sram";
reg = <0x1000 0x8000>;
};
};
dmc: dmc@11200000 {
compatible = "rockchip,rk3228-dmc", "syscon";
reg = <0x11200000 0x3fc
0x12000000 0x400>;
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,msch = <&service_msch>;
rockchip,sram = <&ddr_sram>;
u-boot,dm-pre-reloc;
};
service_msch: syscon@31090000 {
compatible = "rockchip,rk3228-msch", "syscon";
reg = <0x31090000 0x2000>;
u-boot,dm-pre-reloc;
};
};
&cru {
u-boot,dm-pre-reloc;
};
&emmc {
max-frequency = <150000000>;
};
&grf {
u-boot,dm-pre-reloc;
};
&sdmmc {
max-frequency = <150000000>;
};

879
arch/arm/dts/rk322x.dtsi
View File

File diff suppressed because it is too large Load Diff

11
arch/arm/dts/rk3288-evb-u-boot.dtsi
View File

@@ -5,6 +5,17 @@
#include "rk3288-u-boot.dtsi"
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x2>;
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

11
arch/arm/dts/rk3288-evb.dts
View File

@@ -15,17 +15,6 @@
};
};
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x2>;
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
};
&pwm1 {
status = "okay";
};

31
arch/arm/dts/rk3288-firefly-u-boot.dtsi
View File

@@ -5,6 +5,37 @@
#include "rk3288-u-boot.dtsi"
/ {
config {
u-boot,dm-pre-reloc;
u-boot,boot-led = "firefly:green:power";
};
leds {
u-boot,dm-pre-reloc;
work {
u-boot,dm-pre-reloc;
};
power {
u-boot,dm-pre-reloc;
};
};
};
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
/* Add a dummy value to cause of-platdata think this is bytes */
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

17
arch/arm/dts/rk3288-firefly.dts
View File

@@ -13,23 +13,6 @@
chosen {
stdout-path = &uart2;
};
config {
u-boot,dm-pre-reloc;
u-boot,boot-led = "firefly:green:power";
};
};
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
/* Add a dummy value to cause of-platdata think this is bytes */
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&ir {

3
arch/arm/dts/rk3288-firefly.dtsi
View File

@@ -37,11 +37,9 @@
};
leds {
u-boot,dm-pre-reloc;
compatible = "gpio-leds";
work {
u-boot,dm-pre-reloc;
gpios = <&gpio8 1 GPIO_ACTIVE_LOW>;
label = "firefly:blue:user";
linux,default-trigger = "rc-feedback";
@@ -50,7 +48,6 @@
};
power {
u-boot,dm-pre-reloc;
gpios = <&gpio8 2 GPIO_ACTIVE_LOW>;
label = "firefly:green:power";
linux,default-trigger = "default-on";

20
arch/arm/dts/rk3288-miqi-u-boot.dtsi
View File

@@ -4,6 +4,26 @@
*/
#include "rk3288-u-boot.dtsi"
/ {
leds {
u-boot,dm-pre-reloc;
work {
u-boot,dm-pre-reloc;
};
};
};
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&pinctrl {
u-boot,dm-pre-reloc;

11
arch/arm/dts/rk3288-miqi.dts
View File

@@ -14,14 +14,3 @@
stdout-path = "serial2:115200n8";
};
};
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};

2
arch/arm/dts/rk3288-miqi.dtsi
View File

@@ -34,11 +34,9 @@
leds {
u-boot,dm-pre-reloc;
compatible = "gpio-leds";
work {
u-boot,dm-pre-reloc;
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
label = "miqi:green:user";
linux,default-trigger = "default-on";

44
arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi Normal file
View File

@@ -0,0 +1,44 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3288-u-boot.dtsi"
&dmc {
rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
};
&emmc {
u-boot,dm-pre-reloc;
};
&i2c0 {
u-boot,dm-pre-reloc;
rk818: pmic@1c {
u-boot,dm-pre-reloc;
regulators {
u-boot,dm-pre-reloc;
};
};
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};

18
arch/arm/dts/rk3288-phycore-rdk.dts
View File

@@ -112,19 +112,6 @@
};
};
&dmc {
rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xe 0xe>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 5 1>;
};
&gmac {
status = "okay";
};
@@ -175,8 +162,6 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma {
bias-pull-up;
drive-strength = <12>;
@@ -246,8 +231,6 @@
};
&sdmmc {
u-boot,dm-pre-reloc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
@@ -268,7 +251,6 @@
};
&uart2 {
u-boot,dm-pre-reloc;
status = "okay";
};

6
arch/arm/dts/rk3288-phycore-som.dtsi
View File

@@ -149,8 +149,6 @@
&emmc {
status = "okay";
u-boot,dm-pre-reloc;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
@@ -201,8 +199,6 @@
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
clock-frequency = <400000>;
rk818: pmic@1c {
@@ -216,7 +212,6 @@
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
vcc1-supply = <&vdd_sys>;
vcc2-supply = <&vdd_sys>;
@@ -230,7 +225,6 @@
vddio-supply = <&vdd_3v3_io>;
regulators {
u-boot,dm-pre-reloc;
vdd_log: DCDC_REG1 {
regulator-name = "vdd_log";
regulator-always-on;

11
arch/arm/dts/rk3288-popmetal-u-boot.dtsi
View File

@@ -5,6 +5,17 @@
#include "rk3288-u-boot.dtsi"
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&pinctrl {
u-boot,dm-pre-reloc;
};

11
arch/arm/dts/rk3288-popmetal.dts
View File

@@ -15,17 +15,6 @@
};
};
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&pwm1 {
status = "okay";
};

30
arch/arm/dts/rk3288-rock2-square-u-boot.dtsi Normal file
View File

@@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3288-u-boot.dtsi"
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&gpio7 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};

18
arch/arm/dts/rk3288-rock2-square.dts
View File

@@ -96,7 +96,6 @@
};
&sdmmc {
u-boot,dm-pre-reloc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
@@ -139,7 +138,6 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
ir {
ir_int: ir-int {
rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -171,7 +169,6 @@
&uart2 {
status = "okay";
u-boot,dm-pre-reloc;
reg-shift = <2>;
};
@@ -182,18 +179,3 @@
&usb_host0_ehci {
status = "okay";
};
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&gpio7 {
u-boot,dm-pre-reloc;
};

84
arch/arm/dts/rk3288-u-boot.dtsi
View File

@@ -7,10 +7,53 @@
#include "rockchip-optee.dtsi"
/ {
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
gpio5 = &gpio5;
gpio6 = &gpio6;
gpio7 = &gpio7;
gpio8 = &gpio8;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio0;
mmc3 = &sdio1;
};
chosen {
u-boot,spl-boot-order = \
"same-as-spl", &emmc, &sdmmc;
};
dmc: dmc@ff610000 {
compatible = "rockchip,rk3288-dmc", "syscon";
reg = <0xff610000 0x3fc
0xff620000 0x294
0xff630000 0x3fc
0xff640000 0x294>;
clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
<&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
<&cru ARMCLK>;
clock-names = "pclk_ddrupctl0", "pclk_publ0",
"pclk_ddrupctl1", "pclk_publ1",
"arm_clk";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,noc = <&noc>;
rockchip,pmu = <&pmu>;
rockchip,sgrf = <&sgrf>;
rockchip,sram = <&ddr_sram>;
u-boot,dm-pre-reloc;
};
noc: syscon@ffac0000 {
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0xffac0000 0x2000>;
u-boot,dm-pre-reloc;
};
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
@@ -37,7 +80,22 @@
};
#endif
&dmc {
&bus_intmem {
ddr_sram: ddr-sram@1000 {
compatible = "rockchip,rk3288-ddr-sram";
reg = <0x1000 0x4000>;
};
};
&cru {
u-boot,dm-pre-reloc;
};
&gpio7 {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
@@ -49,12 +107,20 @@
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
&uart0 {
clock-frequency = <24000000>;
};
&grf {
u-boot,dm-pre-reloc;
&uart1 {
clock-frequency = <24000000>;
};
&uart2 {
clock-frequency = <24000000>;
};
&uart3 {
clock-frequency = <24000000>;
};
&vopb {
@@ -64,11 +130,3 @@
&vopl {
u-boot,dm-pre-reloc;
};
&noc {
u-boot,dm-pre-reloc;
};
&gpio7 {
u-boot,dm-pre-reloc;
};

14
arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3288-veyron-u-boot.dtsi"
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};

11
arch/arm/dts/rk3288-veyron-jerry.dts
View File

@@ -66,17 +66,6 @@
};
};
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&gpio_keys {
power {
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;

14
arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3288-veyron-u-boot.dtsi"
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x2>;
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
};

11
arch/arm/dts/rk3288-veyron-mickey.dts
View File

@@ -161,17 +161,6 @@
};
};
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x2>;
rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
};
&emmc {
/delete-property/mmc-hs200-1_8v;
};

14
arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
#include "rk3288-veyron-u-boot.dtsi"
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x1>;
rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>;
};

11
arch/arm/dts/rk3288-veyron-minnie.dts
View File

@@ -137,17 +137,6 @@
power-supply = <&backlight_regulator>;
};
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
0x8 0x1f4>;
rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
0x0 0xc3 0x6 0x1>;
rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>;
};
&emmc {
/delete-property/mmc-hs200-1_8v;
};

61
arch/arm/dts/rk3288-veyron-u-boot.dtsi
View File

@@ -5,7 +5,68 @@
#include "rk3288-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = &spi_flash;
};
};
&dmc {
logic-supply = <&vdd_logic>;
rockchip,odt-disable-freq = <333000000>;
rockchip,dll-disable-freq = <333000000>;
rockchip,sr-enable-freq = <333000000>;
rockchip,pd-enable-freq = <666000000>;
rockchip,auto-self-refresh-cnt = <0>;
rockchip,auto-power-down-cnt = <64>;
rockchip,ddr-speed-bin = <21>;
rockchip,trcd = <10>;
rockchip,trp = <10>;
operating-points = <
/* KHz uV */
200000 1050000
333000 1100000
533000 1150000
666000 1200000
>;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio7 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};
&i2c0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&rk808 {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&spi2 {
u-boot,dm-pre-reloc;
};
&spi_flash {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};

39
arch/arm/dts/rk3288-veyron.dtsi
View File

@@ -16,7 +16,6 @@
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = &spi_flash;
};
firmware {
@@ -220,26 +219,6 @@
cpu0-supply = <&vdd_cpu>;
};
&dmc {
logic-supply = <&vdd_logic>;
rockchip,odt-disable-freq = <333000000>;
rockchip,dll-disable-freq = <333000000>;
rockchip,sr-enable-freq = <333000000>;
rockchip,pd-enable-freq = <666000000>;
rockchip,auto-self-refresh-cnt = <0>;
rockchip,auto-power-down-cnt = <64>;
rockchip,ddr-speed-bin = <21>;
rockchip,trcd = <10>;
rockchip,trp = <10>;
operating-points = <
/* KHz uV */
200000 1050000
333000 1100000
533000 1150000
666000 1200000
>;
};
&efuse {
status = "okay";
};
@@ -299,10 +278,8 @@
&spi2 {
status = "okay";
u-boot,dm-pre-reloc;
spi_flash: spiflash@0 {
u-boot,dm-pre-reloc;
compatible = "spidev", "jedec,spi-nor";
spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
reg = <0>;
@@ -315,7 +292,6 @@
clock-frequency = <400000>;
i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
i2c-scl-rising-time-ns = <100>; /* 45ns measured */
u-boot,dm-pre-reloc;
rk808: pmic@1b {
compatible = "rockchip,rk808";
@@ -328,7 +304,6 @@
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
u-boot,dm-pre-reloc;
vcc1-supply = <&vcc33_sys>;
vcc2-supply = <&vcc33_sys>;
@@ -557,7 +532,6 @@
&uart2 {
status = "okay";
u-boot,dm-pre-reloc;
reg-shift = <2>;
};
@@ -601,7 +575,6 @@
};
&pinctrl {
u-boot,dm-pre-reloc;
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
@@ -826,15 +799,3 @@
assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
assigned-clock-parents = <&cru SCLK_OTGPHY0>;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};

51
arch/arm/dts/rk3288.dtsi
View File

@@ -5,7 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3288-cru.h>
#include <dt-bindings/power-domain/rk3288.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/video/rk3288.h>
#include "skeleton.dtsi"
@@ -15,25 +15,12 @@
interrupt-parent = <&gic>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
gpio5 = &gpio5;
gpio6 = &gpio6;
gpio7 = &gpio7;
gpio8 = &gpio8;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio0;
mmc3 = &sdio1;
mshc0 = &emmc;
mshc1 = &sdmmc;
mshc2 = &sdio0;
@@ -323,7 +310,6 @@
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -337,7 +323,6 @@
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -351,7 +336,6 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -364,7 +348,6 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -378,7 +361,6 @@
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
@@ -476,26 +458,6 @@
status = "disabled";
};
dmc: dmc@ff610000 {
compatible = "rockchip,rk3288-dmc", "syscon";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
rockchip,sgrf = <&sgrf>;
rockchip,noc = <&noc>;
reg = <0xff610000 0x3fc
0xff620000 0x294
0xff630000 0x3fc
0xff640000 0x294>;
rockchip,sram = <&ddr_sram>;
clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
<&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
<&cru ARMCLK>;
clock-names = "pclk_ddrupctl0", "pclk_publ0",
"pclk_ddrupctl1", "pclk_publ1",
"arm_clk";
};
i2c0: i2c@ff650000 {
compatible = "rockchip,rk3288-i2c";
reg = <0xff650000 0x1000>;
@@ -570,7 +532,7 @@
status = "disabled";
};
bus_intmem@ff700000 {
bus_intmem: bus_intmem@ff700000 {
compatible = "mmio-sram";
reg = <0xff700000 0x18000>;
#address-cells = <1>;
@@ -580,10 +542,6 @@
compatible = "rockchip,rk3066-smp-sram";
reg = <0x00 0x10>;
};
ddr_sram: ddr-sram@1000 {
compatible = "rockchip,rk3288-ddr-sram";
reg = <0x1000 0x4000>;
};
};
sram@ff720000 {
@@ -912,11 +870,6 @@
status = "disabled";
};
noc: syscon@ffac0000 {
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0xffac0000 0x2000>;
};
efuse: efuse@ffb40000 {
compatible = "rockchip,rk3288-efuse";
reg = <0xffb40000 0x10000>;

8
arch/arm/dts/rk3xxx-u-boot.dtsi
View File

@@ -4,7 +4,7 @@
noc: syscon@10128000 {
compatible = "rockchip,rk3188-noc", "syscon";
reg = <0x10128000 0x2000>;
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
dmc: dmc@20020000 {
@@ -18,16 +18,16 @@
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
rockchip,noc = <&noc>;
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
};
&grf {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pmu {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&uart2 {

8
arch/arm/include/asm/arch-rk3066/boot0.h Normal file
View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

8
arch/arm/include/asm/arch-rk3066/gpio.h Normal file
View File

@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

6
arch/arm/include/asm/arch-rk3066/timer.h Normal file
View File

@@ -0,0 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __ASM_ARCH_TIMER_H__
#define __ASM_ARCH_TIMER_H__
#endif

157
arch/arm/include/asm/arch-rockchip/cru_rk3066.h Normal file
View File

@@ -0,0 +1,157 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2021 Paweł Jarosz <paweljarosz3691@gmail.com>
*/
#ifndef _ASM_ARCH_CRU_RK3066_H
#define _ASM_ARCH_CRU_RK3066_H
#include <linux/bitops.h>
#include <linux/bitfield.h>
#define REG(name, h, l) \
name##_MASK = GENMASK(h, l), \
name##_SHIFT = __bf_shf(name##_MASK)
#define OSC_HZ (24 * 1000 * 1000)
#define APLL_HZ (1416 * 1000000)
#define APLL_SAFE_HZ (600 * 1000000)
#define GPLL_HZ (594 * 1000000)
#define CPLL_HZ (384 * 1000000)
/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
#define CPU_ACLK_HZ 297000000
#define CPU_HCLK_HZ 148500000
#define CPU_PCLK_HZ 74250000
#define CPU_H2P_HZ 74250000
#define PERI_ACLK_HZ 148500000
#define PERI_HCLK_HZ 148500000
#define PERI_PCLK_HZ 74250000
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3066_clk_priv {
struct rk3066_grf *grf;
struct rk3066_cru *cru;
ulong rate;
bool has_bwadj;
};
struct rk3066_cru {
struct rk3066_pll {
u32 con0;
u32 con1;
u32 con2;
u32 con3;
} pll[4];
u32 cru_mode_con;
u32 cru_clksel_con[35];
u32 cru_clkgate_con[10];
u32 reserved1[2];
u32 cru_glb_srst_fst_value;
u32 cru_glb_srst_snd_value;
u32 reserved2[2];
u32 cru_softrst_con[9];
u32 cru_misc_con;
u32 reserved3[2];
u32 cru_glb_cnt_th;
};
check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
/* CRU_CLKSEL0_CON */
enum {
REG(CPU_ACLK_PLL, 8, 8),
CPU_ACLK_PLL_SELECT_APLL = 0,
CPU_ACLK_PLL_SELECT_GPLL,
REG(CORE_PERI_DIV, 7, 6),
REG(A9_CORE_DIV, 4, 0),
};
/* CRU_CLKSEL1_CON */
enum {
REG(AHB2APB_DIV, 15, 14),
REG(CPU_PCLK_DIV, 13, 12),
REG(CPU_HCLK_DIV, 9, 8),
REG(CPU_ACLK_DIV, 2, 0),
};
/* CRU_CLKSEL10_CON */
enum {
REG(PERI_SEL_PLL, 15, 15),
PERI_SEL_CPLL = 0,
PERI_SEL_GPLL,
REG(PERI_PCLK_DIV, 13, 12),
REG(PERI_HCLK_DIV, 9, 8),
REG(PERI_ACLK_DIV, 4, 0),
};
/* CRU_CLKSEL11_CON */
enum {
REG(MMC0_DIV, 5, 0),
};
/* CRU_CLKSEL12_CON */
enum {
REG(UART_PLL, 15, 15),
UART_PLL_SELECT_GENERAL = 0,
UART_PLL_SELECT_CODEC,
REG(EMMC_DIV, 13, 8),
REG(SDIO_DIV, 5, 0),
};
/* CRU_CLKSEL24_CON */
enum {
REG(SARADC_DIV, 15, 8),
};
/* CRU_CLKSEL25_CON */
enum {
REG(SPI1_DIV, 14, 8),
REG(SPI0_DIV, 6, 0),
};
/* CRU_CLKSEL34_CON */
enum {
REG(TSADC_DIV, 15, 0),
};
/* CRU_MODE_CON */
enum {
REG(GPLL_MODE, 13, 12),
REG(CPLL_MODE, 9, 8),
REG(DPLL_MODE, 5, 4),
REG(APLL_MODE, 1, 0),
PLL_MODE_SLOW = 0,
PLL_MODE_NORMAL,
PLL_MODE_DEEP,
};
/* CRU_APLL_CON0 */
enum {
REG(CLKR, 13, 8),
REG(CLKOD, 3, 0),
};
/* CRU_APLL_CON1 */
enum {
REG(CLKF, 12, 0),
};
#endif

210
arch/arm/include/asm/arch-rockchip/grf_rk3066.h Normal file
View File

@@ -0,0 +1,210 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2021 Paweł Jarosz <paweljarosz3691@gmail.com>
*/
#ifndef _ASM_ARCH_GRF_RK3066_H
#define _ASM_ARCH_GRF_RK3066_H
#include <linux/bitops.h>
#include <linux/bitfield.h>
#define REG(name, h, l) \
name##_MASK = GENMASK(h, l), \
name##_SHIFT = __bf_shf(name##_MASK)
struct rk3066_grf_gpio_lh {
u32 l;
u32 h;
};
struct rk3066_grf {
struct rk3066_grf_gpio_lh gpio_dir[7];
struct rk3066_grf_gpio_lh gpio_do[7];
struct rk3066_grf_gpio_lh gpio_en[7];
u32 gpio0a_iomux;
u32 gpio0b_iomux;
u32 gpio0c_iomux;
u32 gpio0d_iomux;
u32 gpio1a_iomux;
u32 gpio1b_iomux;
u32 gpio1c_iomux;
u32 gpio1d_iomux;
u32 gpio2a_iomux;
u32 gpio2b_iomux;
u32 gpio2c_iomux;
u32 gpio2d_iomux;
u32 gpio3a_iomux;
u32 gpio3b_iomux;
u32 gpio3c_iomux;
u32 gpio3d_iomux;
u32 gpio4a_iomux;
u32 gpio4b_iomux;
u32 gpio4c_iomux;
u32 gpio4d_iomux;
u32 reserved0[5];
u32 gpio6b_iomux;
u32 reserved1[2];
struct rk3066_grf_gpio_lh gpio_pull[7];
u32 soc_con0;
u32 soc_con1;
u32 soc_con2;
u32 soc_status0;
u32 dmac1_con[3];
u32 dmac2_con[4];
u32 uoc0_con[3];
u32 uoc1_con[4];
u32 ddrc_con;
u32 ddrc_stat;
u32 reserved2[10];
u32 os_reg[4];
};
check_member(rk3066_grf, os_reg[3], 0x01d4);
/* GRF_GPIO1B_IOMUX */
enum {
REG(GPIO1B1, 2, 2),
GPIO1B1_GPIO = 0,
GPIO1B1_UART2_SOUT,
REG(GPIO1B0, 0, 0),
GPIO1B0_GPIO = 0,
GPIO1B0_UART2_SIN
};
/* GRF_GPIO3B_IOMUX */
enum {
REG(GPIO3B6, 12, 12),
GPIO3B6_GPIO = 0,
GPIO3B6_SDMMC0_DECTN,
REG(GPIO3B5, 10, 10),
GPIO3B5_GPIO = 0,
GPIO3B5_SDMMC0_DATA3,
REG(GPIO3B4, 8, 8),
GPIO3B4_GPIO = 0,
GPIO3B4_SDMMC0_DATA2,
REG(GPIO3B3, 6, 6),
GPIO3B3_GPIO = 0,
GPIO3B3_SDMMC0_DATA1,
REG(GPIO3B2, 4, 4),
GPIO3B2_GPIO = 0,
GPIO3B2_SDMMC0_DATA0,
REG(GPIO3B1, 2, 2),
GPIO3B1_GPIO = 0,
GPIO3B1_SDMMC0_CMD,
REG(GPIO3B0, 0, 0),
GPIO3B0_GPIO = 0,
GPIO3B0_SDMMC0_CLKOUT,
};
/* GRF_SOC_CON0 */
enum {
REG(SMC_MUX_CON, 13, 13),
REG(NOC_REMAP, 12, 12),
REG(EMMC_FLASH_SEL, 11, 11),
REG(TZPC_REVISION, 10, 7),
REG(L2CACHE_ACC, 6, 5),
REG(L2RD_WAIT, 4, 3),
REG(IMEMRD_WAIT, 2, 1),
REG(SOC_REMAP, 0, 0),
};
/* GRF_SOC_CON1 */
enum {
REG(RKI2C4_SEL, 15, 15),
REG(RKI2C3_SEL, 14, 14),
REG(RKI2C2_SEL, 13, 13),
REG(RKI2C1_SEL, 12, 12),
REG(RKI2C0_SEL, 11, 11),
REG(VCODEC_SEL, 10, 10),
REG(PERI_EMEM_PAUSE, 9, 9),
REG(PERI_USB_PAUSE, 8, 8),
REG(SMC_MUX_MODE_0, 6, 6),
REG(SMC_SRAM_MW_0, 5, 4),
REG(SMC_REMAP_0, 3, 3),
REG(SMC_A_GT_M0_SYNC, 2, 2),
REG(EMAC_SPEED, 1, 1),
REG(EMAC_MODE, 0, 0),
};
/* GRF_SOC_CON2 */
enum {
REG(MSCH4_MAINDDR3, 7, 7),
MSCH4_MAINDDR3_DDR3 = 1,
REG(EMAC_NEWRCV_EN, 6, 6),
REG(SW_ADDR15_EN, 5, 5),
REG(SW_ADDR16_EN, 4, 4),
REG(SW_ADDR17_EN, 3, 3),
REG(BANK2_TO_RANK_EN, 2, 2),
REG(RANK_TO_ROW15_EN, 1, 1),
REG(UPCTL_C_ACTIVE_IN, 0, 0),
UPCTL_C_ACTIVE_IN_MAY = 0,
UPCTL_C_ACTIVE_IN_WILL,
};
/* GRF_DDRC_CON0 */
enum {
REG(DTO_LB, 12, 11),
REG(DTO_TE, 10, 9),
REG(DTO_PDR, 8, 7),
REG(DTO_PDD, 6, 5),
REG(DTO_IOM, 4, 3),
REG(DTO_OE, 2, 1),
REG(ATO_AE, 0, 0),
};
#endif

33
arch/arm/mach-rockchip/Kconfig
View File

@@ -35,6 +35,28 @@ config ROCKCHIP_RK3036
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
config ROCKCHIP_RK3066
bool "Support Rockchip RK3066"
select CPU_V7A
select SPL_BOARD_INIT if SPL
select SUPPORT_SPL
select SUPPORT_TPL
select SPL
select TPL
select TPL_ROCKCHIP_BACK_TO_BROM
select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL
imply TPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL
help
The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
video interfaces, several memory options and video codec support.
Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
UART, SPI, I2C and PWMs.
config ROCKCHIP_RK3128
bool "Support Rockchip RK3128"
select CPU_V7A
@@ -339,6 +361,16 @@ config ROCKCHIP_BOOT_MODE_REG
The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
according to the value from this register.
config ROCKCHIP_STIMER
bool "Rockchip STIMER support"
default y
help
Enable Rockchip STIMER support.
config ROCKCHIP_STIMER_BASE
hex
depends on ROCKCHIP_STIMER
config ROCKCHIP_SPL_RESERVE_IRAM
hex "Size of IRAM reserved in SPL"
default 0
@@ -395,6 +427,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3066/Kconfig"
source "arch/arm/mach-rockchip/rk3128/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
source "arch/arm/mach-rockchip/rk322x/Kconfig"

1
arch/arm/mach-rockchip/Makefile
View File

@@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
obj-$(CONFIG_ROCKCHIP_PX30) += px30/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/

3
arch/arm/mach-rockchip/px30/Kconfig
View File

@@ -38,6 +38,9 @@ config TARGET_PX30_CORE
config ROCKCHIP_BOOT_MODE_REG
default 0xff010200
config ROCKCHIP_STIMER_BASE
default 0xff220020
config SYS_SOC
default "px30"

3
arch/arm/mach-rockchip/rk3036/Kconfig
View File

@@ -16,6 +16,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0x200081c8
config ROCKCHIP_STIMER_BASE
default 0x200440a0
config SYS_SOC
default "rk3036"

39
arch/arm/mach-rockchip/rk3066/Kconfig Normal file
View File

@@ -0,0 +1,39 @@
if ROCKCHIP_RK3066
config TARGET_MK808
bool "MK808"
help
MK808 is a RK3066-based board with 1 USB host and 1 USB OTG port,
HDMI and a micro-SD card slot. It also includes on-board NAND
and 1GB of SDRAM.
config ROCKCHIP_BOOT_MODE_REG
default 0x20004040
config SYS_SOC
default "rk3066"
config SYS_MALLOC_F_LEN
default 0x0800
config SPL_LIBCOMMON_SUPPORT
default y
config SPL_LIBGENERIC_SUPPORT
default y
config SPL_SERIAL
default y
config TPL_LIBCOMMON_SUPPORT
default y
config TPL_LIBGENERIC_SUPPORT
default y
config TPL_SERIAL
default y
source "board/rikomagic/mk808/Kconfig"
endif

5
arch/arm/mach-rockchip/rk3066/Makefile Normal file
View File

@@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += clk_rk3066.o
obj-y += rk3066.o
obj-y += syscon_rk3066.o

33
arch/arm/mach-rockchip/rk3066/clk_rk3066.c Normal file
View File

@@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3066.h>
#include <linux/err.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(rockchip_rk3066a_cru), devp);
}
void *rockchip_get_cru(void)
{
struct rk3066_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}

49
arch/arm/mach-rockchip/rk3066/rk3066.c Normal file
View File

@@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3066.h>
#define GRF_BASE 0x20008000
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000",
[BROM_BOOTSOURCE_SD] = "/mmc@10214000",
};
void board_debug_uart_init(void)
{
struct rk3066_grf * const grf = (void *)GRF_BASE;
/* Enable early UART on the RK3066 */
rk_clrsetreg(&grf->gpio1b_iomux,
GPIO1B1_MASK | GPIO1B0_MASK,
GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
}
void spl_board_init(void)
{
if (!IS_ENABLED(CONFIG_SPL_BUILD))
return;
if (IS_ENABLED(CONFIG_SPL_DM_MMC)) {
struct rk3066_grf * const grf = (void *)GRF_BASE;
rk_clrsetreg(&grf->gpio3b_iomux,
GPIO3B0_MASK | GPIO3B1_MASK | GPIO3B2_MASK |
GPIO3B3_MASK | GPIO3B4_MASK | GPIO3B5_MASK |
GPIO3B6_MASK,
GPIO3B0_SDMMC0_CLKOUT << GPIO3B0_SHIFT |
GPIO3B1_SDMMC0_CMD << GPIO3B1_SHIFT |
GPIO3B2_SDMMC0_DATA0 << GPIO3B2_SHIFT |
GPIO3B3_SDMMC0_DATA1 << GPIO3B3_SHIFT |
GPIO3B4_SDMMC0_DATA2 << GPIO3B4_SHIFT |
GPIO3B5_SDMMC0_DATA3 << GPIO3B5_SHIFT |
GPIO3B6_SDMMC0_DECTN << GPIO3B6_SHIFT);
}
}

55
arch/arm/mach-rockchip/rk3066/syscon_rk3066.c Normal file
View File

@@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
*/
#include <common.h>
#include <dm.h>
#include <log.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
static const struct udevice_id rk3066_syscon_ids[] = {
{ .compatible = "rockchip,rk3066-noc", .data = ROCKCHIP_SYSCON_NOC },
{ .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF },
{ .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU },
{ }
};
U_BOOT_DRIVER(syscon_rk3066) = {
.name = "rk3066_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3066_syscon_ids,
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3066_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
return 0;
}
U_BOOT_DRIVER(rockchip_rk3066_noc) = {
.name = "rockchip_rk3066_noc",
.id = UCLASS_SYSCON,
.of_match = rk3066_syscon_ids,
.bind = rk3066_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3066_grf) = {
.name = "rockchip_rk3066_grf",
.id = UCLASS_SYSCON,
.of_match = rk3066_syscon_ids + 1,
.bind = rk3066_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3066_pmu) = {
.name = "rockchip_rk3066_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3066_syscon_ids + 2,
.bind = rk3066_syscon_bind_of_plat,
};
#endif

3
arch/arm/mach-rockchip/rk3128/Kconfig
View File

@@ -16,6 +16,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0x100a0038
config ROCKCHIP_STIMER_BASE
default 0x200440a0
config SYS_SOC
default "rk3128"

4
arch/arm/mach-rockchip/rk3188/rk3188.c
View File

@@ -21,8 +21,8 @@
#define GRF_BASE 0x20008000
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000",
[BROM_BOOTSOURCE_SD] = "/dwmmc@10214000",
[BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000",
[BROM_BOOTSOURCE_SD] = "/mmc@10214000",
};
#ifdef CONFIG_DEBUG_UART_BOARD_INIT

3
arch/arm/mach-rockchip/rk322x/Kconfig
View File

@@ -8,6 +8,9 @@ config TARGET_EVB_RK3229
config ROCKCHIP_BOOT_MODE_REG
default 0x110005c8
config ROCKCHIP_STIMER_BASE
default 0x110d0020
config SYS_SOC
default "rk322x"

4
arch/arm/mach-rockchip/rk322x/rk322x.c
View File

@@ -9,8 +9,8 @@
#include <asm/arch-rockchip/hardware.h>
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/dwmmc@30020000",
[BROM_BOOTSOURCE_SD] = "/dwmmc@30000000",
[BROM_BOOTSOURCE_EMMC] = "/mmc@30020000",
[BROM_BOOTSOURCE_SD] = "/mmc@30000000",
};
#ifdef CONFIG_DEBUG_UART_BOARD_INIT

3
arch/arm/mach-rockchip/rk3288/Kconfig
View File

@@ -148,6 +148,9 @@ config ROCKCHIP_FAST_SPL
config ROCKCHIP_BOOT_MODE_REG
default 0xff730094
config ROCKCHIP_STIMER_BASE
default 0xff810020
config SYS_SOC
default "rk3288"

4
arch/arm/mach-rockchip/rk3288/rk3288.c
View File

@@ -28,8 +28,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define GRF_BASE 0xff770000
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000",
[BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000",
};
#ifdef CONFIG_SPL_BUILD

10
arch/arm/mach-rockchip/rk3308/Kconfig
View File

@@ -8,6 +8,12 @@ config TARGET_ROC_RK3308_CC
bool "Firefly roc-rk3308-cc"
select BOARD_LATE_INIT
config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
config ROCKCHIP_STIMER_BASE
default 0xff1b00a0
config SYS_SOC
default "rk3308"
@@ -17,10 +23,6 @@ config SYS_MALLOC_F_LEN
config SPL_SERIAL
default y
config ROCKCHIP_BOOT_MODE_REG
default 0xff000500
source "board/rockchip/evb_rk3308/Kconfig"
source "board/firefly/firefly-rk3308/Kconfig"

3
arch/arm/mach-rockchip/rk3328/Kconfig
View File

@@ -15,6 +15,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff1005c8
config ROCKCHIP_STIMER_BASE
default 0xff1d0020
config SYS_SOC
default "rk3328"

4
arch/arm/mach-rockchip/rk3328/rk3328.c
View File

@@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define FW_DDR_CON_REG 0xFF7C0040
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000",
[BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000",
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000",
[BROM_BOOTSOURCE_SD] = "/mmc@ff500000",
};
static struct mm_region rk3328_mem_map[] = {

3
arch/arm/mach-rockchip/rk3368/Kconfig
View File

@@ -45,6 +45,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff738200
config ROCKCHIP_STIMER_BASE
default 0xff830020
config SYS_SOC
default "rk3368"

4
arch/arm/mach-rockchip/rk3368/rk3368.c
View File

@@ -58,8 +58,8 @@ static struct mm_region rk3368_mem_map[] = {
struct mm_region *mem_map = rk3368_mem_map;
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
[BROM_BOOTSOURCE_EMMC] = "/mmc@ff0f0000",
[BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000",
};
#ifdef CONFIG_ARCH_EARLY_INIT_R

3
arch/arm/mach-rockchip/rk3399/Kconfig
View File

@@ -125,6 +125,9 @@ endchoice
config ROCKCHIP_BOOT_MODE_REG
default 0xff320300
config ROCKCHIP_STIMER_BASE
default 0xff8680a0
config SYS_SOC
default "rk3399"

3
arch/arm/mach-rockchip/rk3568/Kconfig
View File

@@ -9,6 +9,9 @@ config TARGET_EVB_RK3568
config ROCKCHIP_BOOT_MODE_REG
default 0xfdc20200
config ROCKCHIP_STIMER_BASE
default 0xfdd1c020
config SYS_SOC
default "rk3568"

8
arch/arm/mach-rockchip/spl.c
View File

@@ -71,7 +71,6 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
return MMCSD_MODE_RAW;
}
#if !defined(CONFIG_ROCKCHIP_RK3188)
#define TIMER_LOAD_COUNT_L 0x00
#define TIMER_LOAD_COUNT_H 0x04
#define TIMER_CONTROL_REG 0x10
@@ -81,6 +80,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
__weak void rockchip_stimer_init(void)
{
#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
/* If Timer already enabled, don't re-init it */
u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
@@ -95,8 +95,8 @@ __weak void rockchip_stimer_init(void)
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
TIMER_CONTROL_REG);
}
#endif
}
__weak int board_early_init_f(void)
{
@@ -133,9 +133,9 @@ void board_init_f(ulong dummy)
hang();
}
arch_cpu_init();
#if !defined(CONFIG_ROCKCHIP_RK3188)
rockchip_stimer_init();
#endif
#ifdef CONFIG_SYS_ARCH_TIMER
/* Init ARM arch timer in arch/arm/cpu/armv7/arch_timer.c */
timer_init();

7
arch/arm/mach-rockchip/tpl.c
View File

@@ -15,6 +15,7 @@
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <linux/bitops.h>
#include <linux/kconfig.h>
#if CONFIG_IS_ENABLED(BANNER_PRINT)
#include <timestamp.h>
@@ -29,6 +30,7 @@
__weak void rockchip_stimer_init(void)
{
#if defined(CONFIG_ROCKCHIP_STIMER_BASE)
/* If Timer already enabled, don't re-init it */
u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
@@ -45,6 +47,7 @@ __weak void rockchip_stimer_init(void)
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE +
TIMER_CONTROL_REG);
#endif
}
void board_init_f(ulong dummy)
@@ -75,7 +78,9 @@ void board_init_f(ulong dummy)
/* Init secure timer */
rockchip_stimer_init();
/* Init ARM arch timer in arch/arm/cpu/ */
/* Init ARM arch timer */
if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER))
timer_init();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);

2
board/chipspark/popmetal_rk3288/MAINTAINERS
View File

@@ -1,6 +1,8 @@
POPMETAL-RK3288
M: Lin Huang <hl@rock-chips.com>
S: Maintained
F: arch/arm/dts/rk3288-popmetal.dts
F: arch/arm/dts/rk3288-popmetal-u-boot.dtsi
F: board/chipspark/popmetal_rk3288
F: include/configs/popmetal_rk3288.h
F: configs/popmetal-rk3288_defconfig

17
board/google/veyron/MAINTAINERS
View File

@@ -1,6 +1,8 @@
CHROMEBOOK JERRY BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/arm/dts/rk3288-veyron-jerry.dts
F: arch/arm/dts/rk3288-veyron-jerry-u-boot.dtsi
F: board/google/veyron/
F: include/configs/veyron.h
F: configs/chromebook_jerry_defconfig
@@ -8,6 +10,8 @@ F: configs/chromebook_jerry_defconfig
CHROMEBIT MICKEY BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/arm/dts/rk3288-veyron-mickey.dts
F: arch/arm/dts/rk3288-veyron-mickey-u-boot.dtsi
F: board/google/veyron/
F: include/configs/veyron.h
F: configs/chromebit_mickey_defconfig
@@ -15,6 +19,8 @@ F: configs/chromebit_mickey_defconfig
CHROMEBOOK MINNIE BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/arm/dts/rk3288-veyron-minnie.dts
F: arch/arm/dts/rk3288-veyron-minnie-u-boot.dtsi
F: board/google/veyron/
F: include/configs/veyron.h
F: configs/chromebook_minnie_defconfig
@@ -22,6 +28,17 @@ F: configs/chromebook_minnie_defconfig
CHROMEBOOK SPEEDY BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/arm/dts/rk3288-veyron-speedy.dts
F: arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
F: board/google/veyron/
F: include/configs/veyron.h
F: configs/chromebook_speedy_defconfig
CHROMEBOOK VEYRON COMMON FILES
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/arm/dts/rk3288-veyron.dtsi
F: arch/arm/dts/rk3288-veyron-analog-audio.dtsi
F: arch/arm/dts/rk3288-veyron-broadcom-bluetooth.dtsi
F: arch/arm/dts/rk3288-veyron-chromebook.dtsi
F: arch/arm/dts/rk3288-veyron-edp.dtsi

2
board/mqmaker/miqi_rk3288/MAINTAINERS
View File

@@ -1,6 +1,8 @@
MIQI
M: Jernej Skrabec <jernej.skrabec@siol.net>
S: Maintained
F: arch/arm/dts/rk3288-miqi.dts
F: arch/arm/dts/rk3288-miqi-u-boot.dtsi
F: board/mqmaker/miqi_rk3288
F: include/configs/miqi_rk3288.h
F: configs/miqi-rk3288_defconfig

3
board/phytec/phycore_rk3288/MAINTAINERS
View File

@@ -1,6 +1,9 @@
phyCORE-RK3288
M: Wadim Egorov <w.egorov@phytec.de>
S: Maintained
F: arch/arm/dts/rk3288-phycore-rdk.dts
F: arch/arm/dts/rk3288-phycore-rdk-u-boot.dtsi
F: arch/arm/dts/rk3288-phycore-som.dtsi
F: board/phytec/phycore_rk3288
F: include/configs/phycore_rk3288.h
F: configs/phycore-rk3288_defconfig

3
board/radxa/rock2/MAINTAINERS
View File

@@ -1,6 +1,9 @@
FIREFLY
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: arch/arm/dts/rk3288-rock2-som.dtsi
F: arch/arm/dts/rk3288-rock2-square.dts
F: arch/arm/dts/rk3288-rock2-square-u-boot.dtsi
F: board/radxa/rock2
F: include/configs/rock2.h
F: configs/rock2_defconfig

15
board/rikomagic/mk808/Kconfig Normal file
View File

@@ -0,0 +1,15 @@
if TARGET_MK808
config SYS_BOARD
default "mk808"
config SYS_VENDOR
default "rikomagic"
config SYS_CONFIG_NAME
default "mk808"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

6
board/rikomagic/mk808/MAINTAINERS Normal file
View File

@@ -0,0 +1,6 @@
MK808
M: Johan Jonker <jbx6244@gmail.com>
S: Maintained
F: board/rikomagic/mk808
F: configs/mk808_defconfig
F: include/configs/mk808.h

3
board/rikomagic/mk808/Makefile Normal file
View File

@@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += mk808.o

3
board/rikomagic/mk808/mk808.c Normal file
View File

@@ -0,0 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>

2
board/rockchip/evb_rk3229/MAINTAINERS
View File

@@ -1,6 +1,8 @@
EVB-RK3229
M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
F: arch/arm/dts/rk3229-evb.dts
F: arch/arm/dts/rk3229-evb-u-boot.dtsi
F: board/rockchip/evb_rk3229
F: include/configs/evb_rk3229.h
F: configs/evb-rk3229_defconfig

3
board/rockchip/evb_rk3288/MAINTAINERS
View File

@@ -1,6 +1,9 @@
EVB-RK3288
M: Lin Huang <hl@rock-chips.com>
S: Maintained
F: arch/arm/dts/rk3288-evb.dts
F: arch/arm/dts/rk3288-evb.dtsi
F: arch/arm/dts/rk3288-evb-u-boot.dtsi
F: board/rockchip/evb_rk3288
F: include/configs/evb_rk3288.h
F: configs/evb-rk3288_defconfig

5
board/rockchip/tinker_rk3288/MAINTAINERS
View File

@@ -1,6 +1,11 @@
TINKER-RK3288
M: Lin Huang <hl@rock-chips.com>
S: Maintained
F: arch/arm/dts/rk3288-tinker.dts
F: arch/arm/dts/rk3288-tinker.dtsi
F: arch/arm/dts/rk3288-tinker-s.dts
F: arch/arm/dts/rk3288-tinker-s-u-boot.dtsi
F: arch/arm/dts/rk3288-tinker-u-boot.dtsi
F: board/rockchip/tinker_rk3288
F: include/configs/tinker_rk3288.h
F: configs/tinker-rk3288_defconfig

102
configs/mk808_defconfig Normal file
View File

@@ -0,0 +1,102 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
# CONFIG_SPL_SYS_THUMB_BUILD is not set
# CONFIG_TPL_SYS_THUMB_BUILD is not set
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60408000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x8000
CONFIG_DEFAULT_DEVICE_TREE="rk3066a-mk808"
CONFIG_SPL_TEXT_BASE=0x60000000
CONFIG_ROCKCHIP_RK3066=y
# CONFIG_ROCKCHIP_STIMER is not set
CONFIG_TPL_TEXT_BASE=0x10080C04
CONFIG_TPL_MAX_SIZE=32764
CONFIG_TPL_STACK=0x1008FFFF
CONFIG_TARGET_MK808=y
CONFIG_SPL_STACK_R_ADDR=0x70000000
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_FS_FAT=y
CONFIG_SYS_LOAD_ADDR=0x70800800
CONFIG_SPL_PAYLOAD="u-boot.bin"
CONFIG_DEBUG_UART=y
CONFIG_SD_BOOT=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3066a-mk808.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
CONFIG_TPL_NEEDS_SEPARATE_STACK=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_DTB_PROPS_REMOVE=y
CONFIG_SPL_OF_PLATDATA=y
CONFIG_TPL_OF_PLATDATA=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_TPL_DM=y
# CONFIG_DM_WARN is not set
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_TPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_TPL_SYSCON=y
# CONFIG_SIMPLE_BUS is not set
# CONFIG_SPL_SIMPLE_BUS is not set
# CONFIG_TPL_BLK is not set
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_TPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
# CONFIG_SPL_DM_I2C is not set
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_TPL_RAM=y
CONFIG_DM_RESET=y
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_TPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
# CONFIG_TPL_OF_LIBFDT is not set

1
configs/rock_defconfig
View File

@@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
CONFIG_SPL_TEXT_BASE=0x10080800
CONFIG_ROCKCHIP_RK3188=y
# CONFIG_ROCKCHIP_STIMER is not set
CONFIG_TARGET_ROCK=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
CONFIG_DEBUG_UART_BASE=0x20064000

7
configs/rockpro64-rk3399_defconfig
View File

@@ -28,6 +28,13 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_SATA=y
CONFIG_SATA_SIL=y
CONFIG_SCSI=y
CONFIG_SCSI_AHCI=y
CONFIG_DM_SCSI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y

254
doc/board/rockchip/rockchip.rst
View File

@@ -13,7 +13,7 @@ and it's usage steps.
Rockchip boards
---------------
Rockchip is SoC solutions provider for tablets & PCs, streaming media
Rockchip is a SoC solutions provider for tablets & PCs, streaming media
TV boxes, AI audio & vision, IoT hardware.
A wide range of Rockchip SoCs with associated boards are supported in
@@ -21,9 +21,17 @@ mainline U-Boot.
List of mainline supported Rockchip boards:
* px30
- Rockchip Evb-PX30 (evb-px30)
- Engicam PX30.Core C.TOUCH 2.0 (px30-core-ctouch2-px30)
- Engicam PX30.Core C.TOUCH 2.0 10.1 (px30-core-ctouch2-of10-px30)
- Engicam PX30.Core EDIMM2.2 Starter Kit (px30-core-edimm2.2-px30)
- Firefly Core-PX30-JD4 (firefly-px30)
* rk3036
- Rockchip Evb-RK3036 (evb-rk3036)
- Kylin (kylin_rk3036)
* rk3066
- Rikomagic MK808 (mk808)
* rk3128
- Rockchip Evb-RK3128 (evb-rk3128)
* rk3188
@@ -46,6 +54,8 @@ List of mainline supported Rockchip boards:
* rk3308
- Rockchip Evb-RK3308 (evb-rk3308)
- Roc-cc-RK3308 (roc-cc-rk3308)
* rk3326
- ODROID-GO Advance (odroid-go2)
* rk3328
- Rockchip Evb-RK3328 (evb-rk3328)
- Pine64 Rock64 (rock64-rk3328)
@@ -85,42 +95,73 @@ Building
TF-A
^^^^
TF-A would require to build for ARM64 Rockchip SoCs platforms.
TF-A is required when building ARM64 Rockchip SoCs images.
To build TF-A::
To build TF-A:
git clone https://github.com/ARM-software/arm-trusted-firmware.git
.. code-block:: bash
git clone --depth 1 https://github.com/ARM-software/arm-trusted-firmware.git
cd arm-trusted-firmware
make realclean
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399
cd ..
Specify the PLAT= with desired Rockchip platform to build TF-A for.
U-Boot
^^^^^^
To build rk3328 boards::
.. code-block:: bash
export BL31=/path/to/arm-trusted-firmware/to/bl31.elf
make evb-rk3328_defconfig
make
git clone --depth 1 https://source.denx.de/u-boot/u-boot.git
cd u-boot
To build rk3288 boards::
To build px30 boards:
.. code-block:: bash
export BL31=../arm-trusted-firmware/build/px30/release/bl31/bl31.elf
make evb-px30_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
To build rk3066 boards:
.. code-block:: bash
make mk808_defconfig
make CROSS_COMPILE=arm-linux-gnueabihf-
To build rk3288 boards:
.. code-block:: bash
make evb-rk3288_defconfig
make
make CROSS_COMPILE=arm-linux-gnueabihf-
To build rk3368 boards::
To build rk3328 boards:
export BL31=/path/to/arm-trusted-firmware/to/bl31.elf
.. code-block:: bash
export BL31=../arm-trusted-firmware/build/rk3328/release/bl31/bl31.elf
make evb-rk3328_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
To build rk3368 boards:
.. code-block:: bash
export BL31=../arm-trusted-firmware/build/rk3368/release/bl31/bl31.elf
make evb-px5_defconfig
make
make CROSS_COMPILE=aarch64-linux-gnu-
To build rk3399 boards::
To build rk3399 boards:
export BL31=/path/to/arm-trusted-firmware/to/bl31.elf
.. code-block:: bash
export BL31=../arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf
make evb-rk3399_defconfig
make
make CROSS_COMPILE=aarch64-linux-gnu-
Flashing
--------
@@ -131,10 +172,12 @@ Flashing
SD Card
^^^^^^^
All Rockchip platforms, except rk3128 (which doesn't use SPL) are now
supporting single boot image using binman and pad_cat.
All Rockchip platforms (except rk3128 which doesn't use SPL) are now
supporting a single boot image using binman and pad_cat.
To write an image that boots from an SD card (assumed to be /dev/sda)::
To write an image that boots from a SD card (assumed to be /dev/sda):
.. code-block:: bash
sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64
sync
@@ -144,45 +187,60 @@ eMMC
eMMC flash would probe on mmc0 in most of the Rockchip platforms.
Create GPT partition layout as defined in configurations::
Create GPT partition layout as defined in $partitions:
.. code-block:: bash
mmc dev 0
gpt write mmc 0 $partitions
Connect the USB-OTG cable between host and target device.
Connect the USB-OTG cable between the host and a target device.
Launch fastboot at target::
Launch fastboot on the target with:
.. code-block:: bash
fastboot 0
Upon successful gadget connection,host show the USB device like::
Upon a successful gadget connection the host shows the USB device with:
.. code-block:: bash
lsusb
Bus 001 Device 020: ID 2207:330c Fuzhou Rockchip Electronics Company RK3399 in Mask ROM mode
# Bus 001 Device 020: ID 2207:330c Fuzhou Rockchip Electronics Company RK3399 in Mask ROM mode
Program the flash::
Program the flash with:
.. code-block:: bash
sudo fastboot -i 0x2207 flash loader1 idbloader.img
sudo fastboot -i 0x2207 flash loader2 u-boot.itb
Note: for Rockchip 32-bit platforms the U-Boot proper image
Note:
For Rockchip 32-bit platforms the U-Boot proper image
is u-boot-dtb.img
SPI
^^^
Generating idbloader for SPI boot would require to input a multi image
image format to mkimage tool instead of concerting (like for MMC boot).
The SPI boot method requires the generation of idbloader.img with help of the mkimage tool.
SPL-alone SPI boot image::
SPL-alone SPI boot image:
.. code-block:: bash
./tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin idbloader.img
TPL+SPL SPI boot image::
TPL+SPL SPI boot image:
.. code-block:: bash
./tools/mkimage -n rk3399 -T rkspi -d tpl/u-boot-tpl.bin:spl/u-boot-spl.bin idbloader.img
Copy SPI boot images into SD card and boot from SD::
Copy SPI boot images into SD card and boot from SD:
.. code-block:: bash
sf probe
load mmc 1:1 $kernel_addr_r idbloader.img
@@ -195,35 +253,141 @@ Copy SPI boot images into SD card and boot from SD::
2. Package the image with Rockchip miniloader
---------------------------------------------
Image package with Rockchip miniloader requires robin [1].
Image package with Rockchip miniloader requires rkbin [1].
Create idbloader.img
.. code-block:: bash
.. code-block:: none
cd ..
git clone --depth 1 https://github.com/rockchip-linux/rkbin
Create idbloader.img:
.. code-block:: bash
cd u-boot
./tools/mkimage -n px30 -T rksd -d rkbin/bin/rk33/px30_ddr_333MHz_v1.15.bin idbloader.img
cat rkbin/bin/rk33/px30_miniloader_v1.22.bin >> idbloader.img
./tools/mkimage -n px30 -T rksd -d ../rkbin/bin/rk33/px30_ddr_333MHz_v1.16.bin idbloader.img
cat ../rkbin/bin/rk33/px30_miniloader_v1.31.bin >> idbloader.img
sudo dd if=idbloader.img of=/dev/sda seek=64
Create trust.img
Create trust.img:
.. code-block:: none
.. code-block:: bash
cd rkbin
cd ../rkbin
./tools/trust_merger RKTRUST/PX30TRUST.ini
sudo dd if=trust.img of=/dev/sda seek=24576
Create uboot.img
Create uboot.img [2]:
.. code-block:: none
.. code-block:: bash
rbink/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000
cd ../u-boot
../rkbin/tools/loaderimage --pack --uboot u-boot-dtb.bin uboot.img 0x200000
sudo dd if=uboot.img of=/dev/sda seek=16384
Note:
1. 0x200000 is load address and it's an optional in some platforms.
2. rkbin binaries are kept on updating, so would recommend to use the latest versions.
1. rkbin binaries are regularly updated, so it would be recommended to use the latest version.
2. 0x200000 is a load address and is an option for some platforms.
3. Package the RK3066 image with U-Boot TPL/SPL on NAND
-------------------------------------------------------
Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support.
If all other boot options fail then it enters into a BootROM mode on the USB OTG port.
This method loads TPL/SPL on NAND with U-boot and kernel on SD card.
SD Card
^^^^^^^
U-boot expects a GPT partition map and a boot directory structure with files on the SD card.
.. code-block:: none
Partition Map for MMC device 0 -- Partition Type: EFI
Part Start LBA End LBA Name
1 0x00000040 0x00001f7f "loader1"
2 0x00004000 0x00005fff "loader2"
3 0x00006000 0x00007fff "trust"
4 0x00008000 0x0003ffff "boot"
5 0x00040000 0x00ed7fde "rootfs"
Make sure boot and esp flag are set for the boot partition.
Loader1 partition is not used by RK3066.
Boot partition:
.. code-block:: none
extlinux
extlinux.conf
zImage
rk3066a-mk808.dtb
To write a U-boot image to the SD card (assumed to be /dev/sda):
.. code-block:: bash
sudo dd if=u-boot-dtb.img of=/dev/sda seek=16384
sync
NAND
^^^^
Bring device in BootROM mode:
If bricked and no BootROM mode shows up then connect pin 8 and 9 of the NAND flash
with a needle while reconnecting to the USB OTG port to a PC.
Show connected devices with:
.. code-block:: bash
lsusb
# Bus 001 Device 004: ID 2207:300a Fuzhou Rockchip Electronics Company RK3066 in Mask ROM mode
Create NAND image:
Size of SPL and TPL must be aligned to 2kb.
Program with commands in a bash script ./flash.sh:
.. code-block:: bash
#!/bin/sh
printf "RK30" > tplspl.bin
dd if=u-boot-tpl.bin >> tplspl.bin
truncate -s %2048 tplspl.bin
truncate -s %2048 u-boot-spl.bin
../tools/boot_merger --verbose config-flash.ini
../tools/upgrade_tool ul ./RK30xxLoader_uboot.bin
config-flash.ini:
.. code-block:: none
[CHIP_NAME]
NAME=RK30
[VERSION]
MAJOR=2
MINOR=21
[CODE471_OPTION]
NUM=1
Path1=30_LPDDR2_300MHz_DD.bin
[CODE472_OPTION]
NUM=1
Path1=rk30usbplug.bin
[LOADER_OPTION]
NUM=2
LOADER1=FlashData
LOADER2=FlashBoot
FlashData=tplspl.bin
FlashBoot=u-boot-spl.bin
[OUTPUT]
PATH=RK30xxLoader_uboot.bin
TODO
----
@@ -233,7 +397,5 @@ TODO
- Document SPI flash boot
- Add missing SoC's with it boards list
[1] https://github.com/rockchip-linux/rkbin
.. Jagan Teki <jagan@amarulasolutions.com>
.. Wednesday 28 October 2020 06:47:26 PM IST

21
drivers/adc/rockchip-saradc.c
View File

@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <power/regulator.h>
#define SARADC_CTRL_CHN_MASK GENMASK(2, 0)
#define SARADC_CTRL_POWER_CTRL BIT(3)
@@ -100,8 +101,11 @@ int rockchip_saradc_stop(struct udevice *dev)
int rockchip_saradc_probe(struct udevice *dev)
{
struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
struct rockchip_saradc_priv *priv = dev_get_priv(dev);
struct udevice *vref;
struct clk clk;
int vref_uv;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
@@ -114,6 +118,23 @@ int rockchip_saradc_probe(struct udevice *dev)
priv->active_channel = -1;
ret = device_get_supply_regulator(dev, "vref-supply", &vref);
if (ret) {
printf("can't get vref-supply: %d\n", ret);
return ret;
}
vref_uv = regulator_get_value(vref);
if (vref_uv < 0) {
printf("can't get vref-supply value: %d\n", vref_uv);
return vref_uv;
}
/* VDD supplied by common vref pin */
uc_pdata->vdd_supply = vref;
uc_pdata->vdd_microvolts = vref_uv;
uc_pdata->vss_microvolts = 0;
return 0;
}

1
drivers/clk/rockchip/Makefile
View File

@@ -6,6 +6,7 @@
obj-y += clk_pll.o
obj-$(CONFIG_ROCKCHIP_PX30) += clk_px30.o
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3066) += clk_rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o

3
drivers/clk/rockchip/clk_px30.c
View File

@@ -1403,10 +1403,13 @@ static int px30_clk_enable(struct clk *clk)
{
switch (clk->id) {
case HCLK_HOST:
case HCLK_OTG:
case HCLK_SFC:
case SCLK_GMAC:
case SCLK_GMAC_RX_TX:
case SCLK_MAC_REF:
case SCLK_MAC_REFOUT:
case SCLK_SFC:
case ACLK_GMAC:
case PCLK_GMAC:
case SCLK_GMAC_RMII:

717
drivers/clk/rockchip/clk_rk3066.c Normal file
View File

@@ -0,0 +1,717 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2015 Google, Inc
* (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
*/
#include <bitfield.h>
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3066.h>
#include <asm/arch-rockchip/grf_rk3066.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass-internal.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/log2.h>
#include <linux/stringify.h>
struct rk3066_clk_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3066a_cru dtd;
#endif
};
struct pll_div {
u32 nr;
u32 nf;
u32 no;
};
enum {
VCO_MAX_HZ = 1416U * 1000000,
VCO_MIN_HZ = 300 * 1000000,
OUTPUT_MAX_HZ = 1416U * 1000000,
OUTPUT_MIN_HZ = 30 * 1000000,
FREF_MAX_HZ = 1416U * 1000000,
FREF_MIN_HZ = 30 * 1000,
};
enum {
/* PLL CON0 */
PLL_OD_MASK = GENMASK(3, 0),
/* PLL CON1 */
PLL_NF_MASK = GENMASK(12, 0),
/* PLL CON2 */
PLL_BWADJ_MASK = GENMASK(11, 0),
/* PLL CON3 */
PLL_RESET_SHIFT = 5,
/* GRF_SOC_STATUS0 */
SOCSTS_DPLL_LOCK = BIT(4),
SOCSTS_APLL_LOCK = BIT(5),
SOCSTS_CPLL_LOCK = BIT(6),
SOCSTS_GPLL_LOCK = BIT(7),
};
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _nr, _no) {\
.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
(_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
"divisors on line " __stringify(__LINE__))
/* Keep divisors as low as possible to reduce jitter and power usage. */
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
static int rk3066_clk_set_pll(struct rk3066_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
{
int pll_id = rk_pll_id(clk_id);
struct rk3066_pll *pll = &cru->pll[pll_id];
/* All PLLs have the same VCO and output frequency range restrictions. */
uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
uint output_hz = vco_hz / div->no;
debug("%s: PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", __func__,
(uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
(div->no == 1 || !(div->no % 2)));
/* Enter reset. */
rk_setreg(&pll->con3, BIT(PLL_RESET_SHIFT));
rk_clrsetreg(&pll->con0,
CLKR_MASK | PLL_OD_MASK,
((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
/* Exit reset. */
rk_clrreg(&pll->con3, BIT(PLL_RESET_SHIFT));
return 0;
}
static int rk3066_clk_configure_ddr(struct rk3066_cru *cru, struct rk3066_grf *grf,
unsigned int hz)
{
static const struct pll_div dpll_cfg[] = {
{.nf = 25, .nr = 2, .no = 1},
{.nf = 400, .nr = 9, .no = 2},
{.nf = 500, .nr = 9, .no = 2},
{.nf = 100, .nr = 3, .no = 1},
};
int cfg;
switch (hz) {
case 300000000:
cfg = 0;
break;
case 533000000: /* actually 533.3P MHz */
cfg = 1;
break;
case 666000000: /* actually 666.6P MHz */
cfg = 2;
break;
case 800000000:
cfg = 3;
break;
default:
debug("%s: unsupported SDRAM frequency", __func__);
return -EINVAL;
}
/* Enter PLL slow mode. */
rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
PLL_MODE_SLOW << DPLL_MODE_SHIFT);
rk3066_clk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
/* Wait for PLL lock. */
while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK))
udelay(1);
/* Enter PLL normal mode. */
rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
PLL_MODE_NORMAL << DPLL_MODE_SHIFT);
return 0;
}
static int rk3066_clk_configure_cpu(struct rk3066_cru *cru, struct rk3066_grf *grf,
unsigned int hz)
{
static const struct pll_div apll_cfg[] = {
{.nf = 50, .nr = 1, .no = 2},
{.nf = 59, .nr = 1, .no = 1},
};
int div_core_peri, div_cpu_aclk, cfg;
/*
* We support two possible frequencies, the safe 600MHz
* which will work with default pmic settings and will
* be set to get away from the 24MHz default and
* the maximum of 1.416Ghz, which boards can set if they
* were able to get pmic support for it.
*/
switch (hz) {
case APLL_SAFE_HZ:
cfg = 0;
div_core_peri = 1;
div_cpu_aclk = 3;
break;
case APLL_HZ:
cfg = 1;
div_core_peri = 2;
div_cpu_aclk = 3;
break;
default:
debug("unsupported ARMCLK frequency");
return -EINVAL;
}
/* Enter PLL slow mode. */
rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
PLL_MODE_SLOW << APLL_MODE_SHIFT);
rk3066_clk_set_pll(cru, CLK_ARM, &apll_cfg[cfg]);
/* Wait for PLL lock. */
while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK))
udelay(1);
/* Set divider for peripherals attached to the CPU core. */
rk_clrsetreg(&cru->cru_clksel_con[0],
CORE_PERI_DIV_MASK,
div_core_peri << CORE_PERI_DIV_SHIFT);
/* Set up dependent divisor for cpu_aclk. */
rk_clrsetreg(&cru->cru_clksel_con[1],
CPU_ACLK_DIV_MASK,
div_cpu_aclk << CPU_ACLK_DIV_SHIFT);
/* Enter PLL normal mode. */
rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
PLL_MODE_NORMAL << APLL_MODE_SHIFT);
return hz;
}
static uint32_t rk3066_clk_pll_get_rate(struct rk3066_cru *cru,
enum rk_clk_id clk_id)
{
u32 nr, no, nf;
u32 con;
int pll_id = rk_pll_id(clk_id);
struct rk3066_pll *pll = &cru->pll[pll_id];
static u8 clk_shift[CLK_COUNT] = {
0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
GPLL_MODE_SHIFT
};
uint shift;
con = readl(&cru->cru_mode_con);
shift = clk_shift[clk_id];
switch (FIELD_GET(APLL_MODE_MASK, con >> shift)) {
case PLL_MODE_SLOW:
return OSC_HZ;
case PLL_MODE_NORMAL:
/* normal mode */
con = readl(&pll->con0);
no = bitfield_extract_by_mask(con, CLKOD_MASK) + 1;
nr = bitfield_extract_by_mask(con, CLKR_MASK) + 1;
con = readl(&pll->con1);
nf = bitfield_extract_by_mask(con, CLKF_MASK) + 1;
return (OSC_HZ * nf) / (nr * no);
case PLL_MODE_DEEP:
default:
return 32768;
}
}
static ulong rk3066_clk_mmc_get_clk(struct rk3066_cru *cru, uint gclk_rate,
int periph)
{
uint div;
u32 con;
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]);
div = bitfield_extract_by_mask(con, EMMC_DIV_MASK);
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->cru_clksel_con[11]);
div = bitfield_extract_by_mask(con, MMC0_DIV_MASK);
break;
case HCLK_SDIO:
case SCLK_SDIO:
con = readl(&cru->cru_clksel_con[12]);
div = bitfield_extract_by_mask(con, SDIO_DIV_MASK);
break;
default:
return -EINVAL;
}
return DIV_TO_RATE(gclk_rate, div) / 2;
}
static ulong rk3066_clk_mmc_set_clk(struct rk3066_cru *cru, uint gclk_rate,
int periph, uint freq)
{
int src_clk_div;
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
/* MMC clock by default divides by 2 internally, so need to provide double in CRU. */
src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
assert(src_clk_div <= 0x3f);
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
rk_clrsetreg(&cru->cru_clksel_con[12],
EMMC_DIV_MASK,
src_clk_div << EMMC_DIV_SHIFT);
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_DIV_MASK,
src_clk_div << MMC0_DIV_SHIFT);
break;
case HCLK_SDIO:
case SCLK_SDIO:
rk_clrsetreg(&cru->cru_clksel_con[12],
SDIO_DIV_MASK,
src_clk_div << SDIO_DIV_SHIFT);
break;
default:
return -EINVAL;
}
return rk3066_clk_mmc_get_clk(cru, gclk_rate, periph);
}
static ulong rk3066_clk_spi_get_clk(struct rk3066_cru *cru, uint gclk_rate,
int periph)
{
uint div;
u32 con;
switch (periph) {
case SCLK_SPI0:
con = readl(&cru->cru_clksel_con[25]);
div = bitfield_extract_by_mask(con, SPI0_DIV_MASK);
break;
case SCLK_SPI1:
con = readl(&cru->cru_clksel_con[25]);
div = bitfield_extract_by_mask(con, SPI1_DIV_MASK);
break;
default:
return -EINVAL;
}
return DIV_TO_RATE(gclk_rate, div);
}
static ulong rk3066_clk_spi_set_clk(struct rk3066_cru *cru, uint gclk_rate,
int periph, uint freq)
{
int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
assert(src_clk_div < 128);
switch (periph) {
case SCLK_SPI0:
assert(src_clk_div <= SPI0_DIV_MASK >> SPI0_DIV_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[25],
SPI0_DIV_MASK,
src_clk_div << SPI0_DIV_SHIFT);
break;
case SCLK_SPI1:
assert(src_clk_div <= SPI1_DIV_MASK >> SPI1_DIV_SHIFT);
rk_clrsetreg(&cru->cru_clksel_con[25],
SPI1_DIV_MASK,
src_clk_div << SPI1_DIV_SHIFT);
break;
default:
return -EINVAL;
}
return rk3066_clk_spi_get_clk(cru, gclk_rate, periph);
}
static ulong rk3066_clk_saradc_get_clk(struct rk3066_cru *cru, int periph)
{
u32 div, con;
switch (periph) {
case SCLK_SARADC:
con = readl(&cru->cru_clksel_con[24]);
div = bitfield_extract_by_mask(con, SARADC_DIV_MASK);
break;
case SCLK_TSADC:
con = readl(&cru->cru_clksel_con[34]);
div = bitfield_extract_by_mask(con, TSADC_DIV_MASK);
break;
default:
return -EINVAL;
}
return DIV_TO_RATE(PERI_PCLK_HZ, div);
}
static ulong rk3066_clk_saradc_set_clk(struct rk3066_cru *cru, uint hz,
int periph)
{
int src_clk_div;
src_clk_div = DIV_ROUND_UP(PERI_PCLK_HZ, hz) - 1;
assert(src_clk_div < 128);
switch (periph) {
case SCLK_SARADC:
rk_clrsetreg(&cru->cru_clksel_con[24],
SARADC_DIV_MASK,
src_clk_div << SARADC_DIV_SHIFT);
break;
case SCLK_TSADC:
rk_clrsetreg(&cru->cru_clksel_con[34],
SARADC_DIV_MASK,
src_clk_div << SARADC_DIV_SHIFT);
break;
default:
return -EINVAL;
}
return rk3066_clk_saradc_get_clk(cru, periph);
}
static void rk3066_clk_init(struct rk3066_cru *cru, struct rk3066_grf *grf)
{
u32 aclk_div, hclk_div, pclk_div, h2p_div;
/* Enter PLL slow mode. */
rk_clrsetreg(&cru->cru_mode_con,
GPLL_MODE_MASK |
CPLL_MODE_MASK,
PLL_MODE_SLOW << GPLL_MODE_SHIFT |
PLL_MODE_SLOW << CPLL_MODE_SHIFT);
/* Init PLL. */
rk3066_clk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
rk3066_clk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
/* Wait for PLL lock. */
while ((readl(&grf->soc_status0) &
(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
(SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
udelay(1);
/*
* Select CPU clock PLL source and
* reparent aclk_cpu_pre from APPL to GPLL.
* Set up dependent divisors for PCLK/HCLK and ACLK clocks.
*/
aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
rk_clrsetreg(&cru->cru_clksel_con[0],
CPU_ACLK_PLL_MASK |
A9_CORE_DIV_MASK,
CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT |
aclk_div << A9_CORE_DIV_SHIFT);
hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ);
assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3);
pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ);
assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4);
h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ);
assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3);
rk_clrsetreg(&cru->cru_clksel_con[1],
AHB2APB_DIV_MASK |
CPU_PCLK_DIV_MASK |
CPU_HCLK_DIV_MASK,
h2p_div << AHB2APB_DIV_SHIFT |
pclk_div << CPU_PCLK_DIV_SHIFT |
hclk_div << CPU_HCLK_DIV_SHIFT);
/*
* Select PERI clock PLL source and
* set up dependent divisors for PCLK/HCLK and ACLK clocks.
*/
aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
assert((1 << hclk_div) * PERI_HCLK_HZ ==
PERI_ACLK_HZ && (hclk_div < 0x4));
pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
assert((1 << pclk_div) * PERI_PCLK_HZ ==
PERI_ACLK_HZ && (pclk_div < 0x4));
rk_clrsetreg(&cru->cru_clksel_con[10],
PERI_PCLK_DIV_MASK |
PERI_HCLK_DIV_MASK |
PERI_ACLK_DIV_MASK,
PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
pclk_div << PERI_PCLK_DIV_SHIFT |
hclk_div << PERI_HCLK_DIV_SHIFT |
aclk_div << PERI_ACLK_DIV_SHIFT);
/* Enter PLL normal mode. */
rk_clrsetreg(&cru->cru_mode_con,
GPLL_MODE_MASK |
CPLL_MODE_MASK,
PLL_MODE_NORMAL << GPLL_MODE_SHIFT |
PLL_MODE_NORMAL << CPLL_MODE_SHIFT);
rk3066_clk_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000);
}
static ulong rk3066_clk_get_rate(struct clk *clk)
{
struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
ulong new_rate, gclk_rate;
gclk_rate = rk3066_clk_pll_get_rate(priv->cru, CLK_GENERAL);
switch (clk->id) {
case 1 ... 4:
new_rate = rk3066_clk_pll_get_rate(priv->cru, clk->id);
break;
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO:
new_rate = rk3066_clk_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
clk->id);
break;
case SCLK_SPI0:
case SCLK_SPI1:
new_rate = rk3066_clk_spi_get_clk(priv->cru, PERI_PCLK_HZ,
clk->id);
break;
case PCLK_I2C0:
case PCLK_I2C1:
case PCLK_I2C2:
case PCLK_I2C3:
case PCLK_I2C4:
return gclk_rate;
case SCLK_SARADC:
case SCLK_TSADC:
new_rate = rk3066_clk_saradc_get_clk(priv->cru, clk->id);
break;
case SCLK_TIMER0:
case SCLK_TIMER1:
case SCLK_TIMER2:
case SCLK_UART0:
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
return OSC_HZ;
default:
return -ENOENT;
}
return new_rate;
}
static ulong rk3066_clk_set_rate(struct clk *clk, ulong rate)
{
struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
struct rk3066_cru *cru = priv->cru;
ulong new_rate;
switch (clk->id) {
case PLL_APLL:
new_rate = rk3066_clk_configure_cpu(priv->cru, priv->grf, rate);
break;
case CLK_DDR:
new_rate = rk3066_clk_configure_ddr(priv->cru, priv->grf, rate);
break;
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO:
new_rate = rk3066_clk_mmc_set_clk(cru, PERI_HCLK_HZ,
clk->id, rate);
break;
case SCLK_SPI0:
case SCLK_SPI1:
new_rate = rk3066_clk_spi_set_clk(cru, PERI_PCLK_HZ,
clk->id, rate);
break;
case SCLK_SARADC:
case SCLK_TSADC:
new_rate = rk3066_clk_saradc_set_clk(cru, rate, clk->id);
break;
case PLL_CPLL:
case PLL_GPLL:
case ACLK_CPU:
case HCLK_CPU:
case PCLK_CPU:
case ACLK_PERI:
case HCLK_PERI:
case PCLK_PERI:
return 0;
default:
return -ENOENT;
}
return new_rate;
}
static int rk3066_clk_enable(struct clk *clk)
{
struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case HCLK_NANDC0:
rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(9));
break;
case HCLK_SDMMC:
rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(10));
break;
case HCLK_SDIO:
rk_clrreg(&priv->cru->cru_clkgate_con[5], BIT(11));
break;
}
return 0;
}
static int rk3066_clk_disable(struct clk *clk)
{
struct rk3066_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case HCLK_NANDC0:
rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(9));
break;
case HCLK_SDMMC:
rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(10));
break;
case HCLK_SDIO:
rk_setreg(&priv->cru->cru_clkgate_con[5], BIT(11));
break;
}
return 0;
}
static struct clk_ops rk3066_clk_ops = {
.disable = rk3066_clk_disable,
.enable = rk3066_clk_enable,
.get_rate = rk3066_clk_get_rate,
.set_rate = rk3066_clk_set_rate,
};
static int rk3066_clk_of_to_plat(struct udevice *dev)
{
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct rk3066_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
}
return 0;
}
static int rk3066_clk_probe(struct udevice *dev)
{
struct rk3066_clk_priv *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(priv->grf))
return PTR_ERR(priv->grf);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3066_clk_plat *plat = dev_get_plat(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
if (IS_ENABLED(CONFIG_TPL_BUILD)) {
rk3066_clk_init(priv->cru, priv->grf);
/* Init CPU frequency. */
rk3066_clk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ);
}
return 0;
}
static int rk3066_clk_bind(struct udevice *dev)
{
struct udevice *sys_child;
struct sysreset_reg *priv;
int reg_offset, ret;
/* The reset driver does not have a device node, so bind it here. */
ret = device_bind(dev, DM_DRIVER_GET(sysreset_rockchip), "sysreset",
NULL, ofnode_null(), &sys_child);
if (ret) {
dev_dbg(dev, "Warning: No sysreset driver: ret=%d\n", ret);
} else {
priv = malloc(sizeof(struct sysreset_reg));
priv->glb_srst_fst_value = offsetof(struct rk3066_cru,
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3066_cru,
cru_glb_srst_snd_value);
dev_set_priv(sys_child, priv);
}
if (CONFIG_IS_ENABLED(RESET_ROCKCHIP)) {
reg_offset = offsetof(struct rk3066_cru, cru_softrst_con[0]);
ret = rockchip_reset_bind(dev, reg_offset, 9);
if (ret)
dev_dbg(dev, "Warning: software reset driver bind failed\n");
}
return 0;
}
static const struct udevice_id rk3066_clk_ids[] = {
{ .compatible = "rockchip,rk3066a-cru" },
{ }
};
U_BOOT_DRIVER(rockchip_rk3066a_cru) = {
.name = "rockchip_rk3066a_cru",
.id = UCLASS_CLK,
.ops = &rk3066_clk_ops,
.probe = rk3066_clk_probe,
.bind = rk3066_clk_bind,
.of_match = rk3066_clk_ids,
.of_to_plat = rk3066_clk_of_to_plat,
.priv_auto = sizeof(struct rk3066_clk_priv),
.plat_auto = sizeof(struct rk3066_clk_plat),
};

7
drivers/mmc/rockchip_dw_mmc.c
View File

@@ -119,15 +119,15 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
host->priv = dev;
host->dev_index = 0;
priv->fifo_depth = dtplat->fifo_depth;
priv->fifo_mode = 0;
priv->fifo_mode = dtplat->u_boot_spl_fifo_mode;
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = dtplat->max_frequency;
ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
ret = clk_get_by_phandle(dev, &dtplat->clocks[1], &priv->clk);
if (ret < 0)
return ret;
#else
ret = clk_get_by_index(dev, 0, &priv->clk);
ret = clk_get_by_index(dev, 1, &priv->clk);
if (ret < 0)
return ret;
#endif
@@ -180,5 +180,6 @@ U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = {
.plat_auto = sizeof(struct rockchip_mmc_plat),
};
DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk2928_dw_mshc)
DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)

2
drivers/mmc/rockchip_sdhci.c
View File

@@ -227,7 +227,7 @@ static int rk3399_emmc_get_phy(struct udevice *dev)
}
grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (grf_base < 0) {
if (IS_ERR_OR_NULL(grf_base)) {
printf("%s Get syscon grf failed", __func__);
return -ENODEV;
}

1
drivers/pinctrl/rockchip/Makefile
View File

@@ -5,6 +5,7 @@
obj-y += pinctrl-rockchip-core.o
obj-$(CONFIG_ROCKCHIP_PX30) += pinctrl-px30.o
obj-$(CONFIG_ROCKCHIP_RK3036) += pinctrl-rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3066) += pinctrl-rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3128) += pinctrl-rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) += pinctrl-rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) += pinctrl-rk322x.o

112
drivers/pinctrl/rockchip/pinctrl-rk3066.c Normal file
View File

@@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <regmap.h>
#include <syscon.h>
#include <linux/bitops.h>
#include "pinctrl-rockchip.h"
static int rk3066_pinctrl_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
u8 bit;
u32 data;
regmap = priv->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
data = (mask << (bit + 16));
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
return ret;
}
#define RK3066_PULL_OFFSET 0x118
#define RK3066_PULL_PINS_PER_REG 16
#define RK3066_PULL_BANK_STRIDE 8
static void rk3066_pinctrl_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl_priv *priv = bank->priv;
*regmap = priv->regmap_base;
*reg = RK3066_PULL_OFFSET;
*reg += bank->bank_num * RK3066_PULL_BANK_STRIDE;
*reg += (pin_num / RK3066_PULL_PINS_PER_REG) * 4;
*bit = pin_num % RK3066_PULL_PINS_PER_REG;
};
static int rk3066_pinctrl_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct regmap *regmap;
int reg, ret;
u8 bit;
u32 data;
if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
pull != PIN_CONFIG_BIAS_DISABLE)
return -EOPNOTSUPP;
rk3066_pinctrl_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
data = BIT(bit + 16);
if (pull == PIN_CONFIG_BIAS_DISABLE)
data |= BIT(bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
static struct rockchip_pin_bank rk3066_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
PIN_BANK(4, 32, "gpio4"),
PIN_BANK(6, 16, "gpio6"),
};
static struct rockchip_pin_ctrl rk3066_pin_ctrl = {
.pin_banks = rk3066_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066_pin_banks),
.grf_mux_offset = 0xa8,
.set_mux = rk3066_pinctrl_set_mux,
.set_pull = rk3066_pinctrl_set_pull,
};
static const struct udevice_id rk3066_pinctrl_ids[] = {
{
.compatible = "rockchip,rk3066a-pinctrl",
.data = (ulong)&rk3066_pin_ctrl
},
{}
};
U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = {
.name = "rockchip_rk3066a_pinctrl",
.id = UCLASS_PINCTRL,
.ops = &rockchip_pinctrl_ops,
.probe = rockchip_pinctrl_probe,
#if CONFIG_IS_ENABLED(OF_REAL)
.bind = dm_scan_fdt_dev,
#endif
.of_match = rk3066_pinctrl_ids,
.priv_auto = sizeof(struct rockchip_pinctrl_priv),
};

1
drivers/ram/rockchip/Makefile
View File

@@ -5,6 +5,7 @@
obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3066) = sdram_rk3066.o
obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o
obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o

892
drivers/ram/rockchip/sdram_rk3066.c Normal file
View File

@@ -0,0 +1,892 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* (C) Copyright 2015 Google, Inc
* Copyright 2014 Rockchip Inc.
*
* Adapted from the very similar rk3188 ddr init.
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <hang.h>
#include <init.h>
#include <log.h>
#include <ram.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3066.h>
#include <asm/arch-rockchip/ddr_rk3188.h>
#include <asm/arch-rockchip/grf_rk3066.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/pmu_rk3188.h>
#include <asm/arch-rockchip/sdram_rk3288.h>
#include <asm/arch-rockchip/sdram.h>
#include <linux/delay.h>
#include <linux/err.h>
struct rk3066_dmc_chan_info {
struct rk3288_ddr_pctl *pctl;
struct rk3288_ddr_publ *publ;
struct rk3188_msch *msch;
};
struct rk3066_dmc_dram_info {
struct rk3066_dmc_chan_info chan[1];
struct ram_info info;
struct clk ddr_clk;
struct rk3066_cru *cru;
struct rk3066_grf *grf;
struct rk3066_sgrf *sgrf;
struct rk3188_pmu *pmu;
};
struct rk3066_dmc_sdram_params {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3066_dmc of_plat;
#endif
struct rk3288_sdram_channel ch[2];
struct rk3288_sdram_pctl_timing pctl_timing;
struct rk3288_sdram_phy_timing phy_timing;
struct rk3288_base_params base;
int num_channels;
struct regmap *map;
};
const int rk3066_dmc_ddrconf_table[] = {
/*
* [5:4] row(13+n)
* [1:0] col(9+n), assume bw=2
* row col,bw
*/
0,
(2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
(1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
(0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT,
(2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
(1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
(0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT,
(1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
(0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT,
0,
0,
0,
0,
0,
0,
0,
};
#define TEST_PATTERN 0x5aa5f00f
#define DQS_GATE_TRAINING_ERROR_RANK0 BIT(4)
#define DQS_GATE_TRAINING_ERROR_RANK1 BIT(5)
static void rk3066_dmc_copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
for (i = 0; i < n / sizeof(u32); i++) {
writel(*src, dest);
src++;
dest++;
}
}
static void rk3066_dmc_ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy)
{
u32 phy_ctl_srstn_shift = 13;
u32 ctl_psrstn_shift = 11;
u32 ctl_srstn_shift = 10;
u32 phy_psrstn_shift = 9;
u32 phy_srstn_shift = 8;
rk_clrsetreg(&cru->cru_softrst_con[5],
1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
1 << phy_srstn_shift,
phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
phy << phy_srstn_shift);
}
static void rk3066_dmc_ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n)
{
u32 phy_ctl_srstn_shift = 13;
rk_clrsetreg(&cru->cru_softrst_con[5],
1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
}
static void rk3066_dmc_phy_pctrl_reset(struct rk3066_cru *cru,
struct rk3288_ddr_publ *publ,
int channel)
{
int i;
rk3066_dmc_ddr_reset(cru, channel, 1, 1);
udelay(1);
clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
for (i = 0; i < 4; i++)
clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
udelay(10);
setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
for (i = 0; i < 4; i++)
setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
udelay(10);
rk3066_dmc_ddr_reset(cru, channel, 1, 0);
udelay(10);
rk3066_dmc_ddr_reset(cru, channel, 0, 0);
udelay(10);
}
static void rk3066_dmc_phy_dll_bypass_set(struct rk3288_ddr_publ *publ, u32 freq)
{
int i;
if (freq <= 250000000) {
if (freq <= 150000000)
clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
else
setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
for (i = 0; i < 4; i++)
setbits_le32(&publ->datx8[i].dxdllcr,
DXDLLCR_DLLDIS);
setbits_le32(&publ->pir, PIR_DLLBYP);
} else {
clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
for (i = 0; i < 4; i++) {
clrbits_le32(&publ->datx8[i].dxdllcr,
DXDLLCR_DLLDIS);
}
clrbits_le32(&publ->pir, PIR_DLLBYP);
}
}
static void rk3066_dmc_dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
{
writel(DFI_INIT_START, &pctl->dfistcfg0);
writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
&pctl->dfistcfg1);
writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
&pctl->dfilpcfg0);
writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
writel(1, &pctl->dfitphyupdtype0);
/* CS0 and CS1 write ODT enable. */
writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
&pctl->dfiodtcfg);
/* Write ODT length. */
writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
/* Disable phyupd and ctrlupd. */
writel(0, &pctl->dfiupdcfg);
}
static void rk3066_dmc_ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel,
bool ddr3_mode)
{
uint mask, val;
mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
rk_clrsetreg(&grf->soc_con2, mask, val);
}
static void rk3066_dmc_ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable)
{
uint mask, val;
mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
val = enable << RANK_TO_ROW15_EN_SHIFT;
rk_clrsetreg(&grf->soc_con2, mask, val);
}
static void rk3066_dmc_pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
struct rk3066_dmc_sdram_params *sdram_params,
struct rk3066_grf *grf)
{
rk3066_dmc_copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
sizeof(sdram_params->pctl_timing));
switch (sdram_params->base.dramtype) {
case DDR3:
if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
writel(sdram_params->pctl_timing.tcl - 3,
&pctl->dfitrddataen);
} else {
writel(sdram_params->pctl_timing.tcl - 2,
&pctl->dfitrddataen);
}
writel(sdram_params->pctl_timing.tcwl - 1,
&pctl->dfitphywrlat);
writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
&pctl->mcfg);
rk3066_dmc_ddr_set_ddr3_mode(grf, channel, true);
break;
}
setbits_le32(&pctl->scfg, 1);
}
static void rk3066_dmc_phy_cfg(const struct rk3066_dmc_chan_info *chan, int channel,
struct rk3066_dmc_sdram_params *sdram_params)
{
struct rk3288_ddr_publ *publ = chan->publ;
struct rk3188_msch *msch = chan->msch;
uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
u32 dinit2;
int i;
dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
/* Set DDR PHY timing. */
rk3066_dmc_copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
sizeof(sdram_params->phy_timing));
writel(sdram_params->base.noc_timing, &msch->ddrtiming);
writel(0x3f, &msch->readlatency);
writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
&publ->ptr[1]);
writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
&publ->ptr[2]);
switch (sdram_params->base.dramtype) {
case DDR3:
clrbits_le32(&publ->pgcr, 0x1f);
clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
DDRMD_DDR3 << DDRMD_SHIFT);
break;
}
if (sdram_params->base.odt) {
/* Enable dynamic RTT. */
for (i = 0; i < 4; i++)
setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
} else {
/* Disable dynamic RTT. */
for (i = 0; i < 4; i++)
clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
}
}
static void rk3066_dmc_phy_init(struct rk3288_ddr_publ *publ)
{
setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
| PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
udelay(1);
while ((readl(&publ->pgsr) &
(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
;
}
static void rk3066_dmc_send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
u32 cmd, u32 arg)
{
writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
udelay(1);
while (readl(&pctl->mcmd) & START_CMD)
;
}
static inline void rk3066_dmc_send_command_op(struct rk3288_ddr_pctl *pctl,
u32 rank, u32 cmd, u32 ma, u32 op)
{
rk3066_dmc_send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
(op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
}
static void rk3066_dmc_memory_init(struct rk3288_ddr_publ *publ,
u32 dramtype)
{
setbits_le32(&publ->pir,
(PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
| PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
| (dramtype == DDR3 ? PIR_DRAMRST : 0)));
udelay(1);
while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
!= (PGSR_IDONE | PGSR_DLDONE))
;
}
static void rk3066_dmc_move_to_config_state(struct rk3288_ddr_publ *publ,
struct rk3288_ddr_pctl *pctl)
{
unsigned int state;
while (1) {
state = readl(&pctl->stat) & PCTL_STAT_MSK;
switch (state) {
case LOW_POWER:
writel(WAKEUP_STATE, &pctl->sctl);
while ((readl(&pctl->stat) & PCTL_STAT_MSK)
!= ACCESS)
;
/* Wait DLL lock. */
while ((readl(&publ->pgsr) & PGSR_DLDONE)
!= PGSR_DLDONE)
;
/*
* If at low power state we need to wakeup first
* and then enter the config.
*/
fallthrough;
case ACCESS:
fallthrough;
case INIT_MEM:
writel(CFG_STATE, &pctl->sctl);
while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
;
break;
case CONFIG:
return;
default:
break;
}
}
}
static void rk3066_dmc_set_bandwidth_ratio(const struct rk3066_dmc_chan_info *chan, int channel,
u32 n, struct rk3066_grf *grf)
{
struct rk3288_ddr_pctl *pctl = chan->pctl;
struct rk3288_ddr_publ *publ = chan->publ;
struct rk3188_msch *msch = chan->msch;
if (n == 1) {
setbits_le32(&pctl->ppcfg, 1);
setbits_le32(&msch->ddrtiming, 1 << 31);
/* Data byte disable. */
clrbits_le32(&publ->datx8[2].dxgcr, 1);
clrbits_le32(&publ->datx8[3].dxgcr, 1);
/* Disable DLL. */
setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
} else {
clrbits_le32(&pctl->ppcfg, 1);
clrbits_le32(&msch->ddrtiming, 1 << 31);
/* Data byte enable.*/
setbits_le32(&publ->datx8[2].dxgcr, 1);
setbits_le32(&publ->datx8[3].dxgcr, 1);
/* Enable DLL. */
clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
/* Reset DLL. */
clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
udelay(10);
setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
}
setbits_le32(&pctl->dfistcfg0, 1 << 2);
}
static int rk3066_dmc_data_training(const struct rk3066_dmc_chan_info *chan, int channel,
struct rk3066_dmc_sdram_params *sdram_params)
{
unsigned int j;
int ret = 0;
u32 rank;
int i;
u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
struct rk3288_ddr_publ *publ = chan->publ;
struct rk3288_ddr_pctl *pctl = chan->pctl;
/* Disable auto refresh. */
writel(0, &pctl->trefi);
if (sdram_params->base.dramtype != LPDDR3)
setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
rank = sdram_params->ch[channel].rank | 1;
for (j = 0; j < ARRAY_SIZE(step); j++) {
/*
* Trigger QSTRN and RVTRN.
* Clear DTDONE status.
*/
setbits_le32(&publ->pir, PIR_CLRSR);
/* Trigger DTT. */
setbits_le32(&publ->pir,
PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
PIR_CLRSR);
udelay(1);
/* Wait echo byte DTDONE. */
while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
!= rank)
;
while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
!= rank)
;
if (!(readl(&pctl->ppcfg) & 1)) {
while ((readl(&publ->datx8[2].dxgsr[0])
& rank) != rank)
;
while ((readl(&publ->datx8[3].dxgsr[0])
& rank) != rank)
;
}
if (readl(&publ->pgsr) &
(PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
ret = -1;
break;
}
}
/* Send some auto refresh to complement the lost while DTT. */
for (i = 0; i < (rank > 1 ? 8 : 4); i++)
rk3066_dmc_send_command(pctl, rank, REF_CMD, 0);
if (sdram_params->base.dramtype != LPDDR3)
clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
/* Resume auto refresh. */
writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
return ret;
}
static void rk3066_dmc_move_to_access_state(const struct rk3066_dmc_chan_info *chan)
{
struct rk3288_ddr_publ *publ = chan->publ;
struct rk3288_ddr_pctl *pctl = chan->pctl;
unsigned int state;
while (1) {
state = readl(&pctl->stat) & PCTL_STAT_MSK;
switch (state) {
case LOW_POWER:
if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
LP_TRIG_MASK) == 1)
return;
writel(WAKEUP_STATE, &pctl->sctl);
while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
;
/* Wait DLL lock. */
while ((readl(&publ->pgsr) & PGSR_DLDONE)
!= PGSR_DLDONE)
;
break;
case INIT_MEM:
writel(CFG_STATE, &pctl->sctl);
while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
;
fallthrough;
case CONFIG:
writel(GO_STATE, &pctl->sctl);
while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
;
break;
case ACCESS:
return;
default:
break;
}
}
}
static void rk3066_dmc_dram_cfg_rbc(const struct rk3066_dmc_chan_info *chan, u32 chnum,
struct rk3066_dmc_sdram_params *sdram_params)
{
struct rk3288_ddr_publ *publ = chan->publ;
if (sdram_params->ch[chnum].bk == 3)
clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
1 << PDQ_SHIFT);
else
clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
}
static void rk3066_dmc_dram_all_config(const struct rk3066_dmc_dram_info *dram,
struct rk3066_dmc_sdram_params *sdram_params)
{
unsigned int chan;
u32 sys_reg = 0;
sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
for (chan = 0; chan < sdram_params->num_channels; chan++) {
const struct rk3288_sdram_channel *info =
&sdram_params->ch[chan];
sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
rk3066_dmc_dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
}
if (sdram_params->ch[0].rank == 2)
rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0);
else
rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1);
writel(sys_reg, &dram->pmu->sys_reg[2]);
}
static int rk3066_dmc_sdram_rank_bw_detect(struct rk3066_dmc_dram_info *dram, int channel,
struct rk3066_dmc_sdram_params *sdram_params)
{
int reg;
int need_trainig = 0;
const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
struct rk3288_ddr_publ *publ = chan->publ;
rk3066_dmc_ddr_rank_2_row15en(dram->grf, 0);
if (rk3066_dmc_data_training(chan, channel, sdram_params) < 0) {
debug("first data training fail!\n");
reg = readl(&publ->datx8[0].dxgsr[0]);
/* Check the result for rank 0. */
if (channel == 0 && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
debug("data training fail!\n");
return -EIO;
}
/* Check the result for rank 1. */
if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
sdram_params->ch[channel].rank = 1;
clrsetbits_le32(&publ->pgcr, 0xF << 18,
sdram_params->ch[channel].rank << 18);
need_trainig = 1;
}
reg = readl(&publ->datx8[2].dxgsr[0]);
if (reg & (1 << 4)) {
sdram_params->ch[channel].bw = 1;
rk3066_dmc_set_bandwidth_ratio(chan, channel,
sdram_params->ch[channel].bw,
dram->grf);
need_trainig = 1;
}
}
/* Assume that the die bit width is equel to the chip bit width. */
sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
if (need_trainig &&
(rk3066_dmc_data_training(chan, channel, sdram_params) < 0)) {
if (sdram_params->base.dramtype == LPDDR3) {
rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 1);
udelay(10);
rk3066_dmc_ddr_phy_ctl_reset(dram->cru, channel, 0);
udelay(10);
}
debug("2nd data training failed!");
return -EIO;
}
return 0;
}
static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, int channel,
struct rk3066_dmc_sdram_params *sdram_params)
{
int row, col;
unsigned int addr;
const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
struct rk3288_ddr_pctl *pctl = chan->pctl;
struct rk3288_ddr_publ *publ = chan->publ;
int ret = 0;
/* Detect col. */
for (col = 11; col >= 9; col--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE +
(1 << (col + sdram_params->ch[channel].bw - 1));
writel(TEST_PATTERN, addr);
if ((readl(addr) == TEST_PATTERN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
break;
}
if (col == 8) {
debug("Col detect error\n");
ret = -EINVAL;
goto out;
} else {
sdram_params->ch[channel].col = col;
}
rk3066_dmc_ddr_rank_2_row15en(dram->grf, 1);
rk3066_dmc_move_to_config_state(publ, pctl);
writel(1, &chan->msch->ddrconf);
rk3066_dmc_move_to_access_state(chan);
/* Detect row, max 15, min13 for rk3066 */
for (row = 16; row >= 13; row--) {
writel(0, CONFIG_SYS_SDRAM_BASE);
addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
writel(TEST_PATTERN, addr);
if ((readl(addr) == TEST_PATTERN) &&
(readl(CONFIG_SYS_SDRAM_BASE) == 0))
break;
}
if (row == 12) {
debug("Row detect error\n");
ret = -EINVAL;
} else {
sdram_params->ch[channel].cs1_row = row;
sdram_params->ch[channel].row_3_4 = 0;
debug("chn %d col %d, row %d\n", channel, col, row);
sdram_params->ch[channel].cs0_row = row;
}
out:
return ret;
}
static int rk3066_dmc_sdram_get_niu_config(struct rk3066_dmc_sdram_params *sdram_params)
{
int i, tmp, size, ret = 0;
tmp = sdram_params->ch[0].col - 9;
tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4);
size = ARRAY_SIZE(rk3066_dmc_ddrconf_table) / sizeof(rk3066_dmc_ddrconf_table[0]);
for (i = 0; i < size; i++)
if (tmp == rk3066_dmc_ddrconf_table[i])
break;
if (i >= size) {
debug("niu config not found\n");
ret = -EINVAL;
} else {
debug("niu config %d\n", i);
sdram_params->base.ddrconfig = i;
}
return ret;
}
static int rk3066_dmc_sdram_init(struct rk3066_dmc_dram_info *dram,
struct rk3066_dmc_sdram_params *sdram_params)
{
int channel;
int zqcr;
int ret;
if ((sdram_params->base.dramtype == DDR3 &&
sdram_params->base.ddr_freq > 800000000)) {
debug("SDRAM frequency is too high!");
return -E2BIG;
}
ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
if (ret) {
debug("Could not set DDR clock\n");
return ret;
}
for (channel = 0; channel < 1; channel++) {
const struct rk3066_dmc_chan_info *chan = &dram->chan[channel];
struct rk3288_ddr_pctl *pctl = chan->pctl;
struct rk3288_ddr_publ *publ = chan->publ;
rk3066_dmc_phy_pctrl_reset(dram->cru, publ, channel);
rk3066_dmc_phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
rk3066_dmc_dfi_cfg(pctl, sdram_params->base.dramtype);
rk3066_dmc_pctl_cfg(channel, pctl, sdram_params, dram->grf);
rk3066_dmc_phy_cfg(chan, channel, sdram_params);
rk3066_dmc_phy_init(publ);
writel(POWER_UP_START, &pctl->powctl);
while (!(readl(&pctl->powstat) & POWER_UP_DONE))
;
rk3066_dmc_memory_init(publ, sdram_params->base.dramtype);
rk3066_dmc_move_to_config_state(publ, pctl);
/* Use 32bit bus width for detection. */
sdram_params->ch[channel].bw = 2;
rk3066_dmc_set_bandwidth_ratio(chan, channel,
sdram_params->ch[channel].bw, dram->grf);
/*
* set cs, using n=3 for detect
* CS0, n=1
* CS1, n=2
* CS0 & CS1, n = 3
*/
sdram_params->ch[channel].rank = 2;
clrsetbits_le32(&publ->pgcr, 0xF << 18,
(sdram_params->ch[channel].rank | 1) << 18);
/* DS=40ohm,ODT=155ohm */
zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
0x19 << PD_OUTPUT_SHIFT;
writel(zqcr, &publ->zq1cr[0]);
writel(zqcr, &publ->zq0cr[0]);
/* Detect the rank and bit-width with data-training. */
writel(1, &chan->msch->ddrconf);
rk3066_dmc_sdram_rank_bw_detect(dram, channel, sdram_params);
if (sdram_params->base.dramtype == LPDDR3) {
u32 i;
writel(0, &pctl->mrrcfg0);
for (i = 0; i < 17; i++)
rk3066_dmc_send_command_op(pctl, 1, MRR_CMD, i, 0);
}
writel(4, &chan->msch->ddrconf);
rk3066_dmc_move_to_access_state(chan);
/* DDR3 and LPDDR3 are always 8 bank, no need to detect. */
sdram_params->ch[channel].bk = 3;
/* Detect Col and Row number. */
ret = rk3066_dmc_sdram_col_row_detect(dram, channel, sdram_params);
if (ret)
goto error;
}
/* Find NIU DDR configuration. */
ret = rk3066_dmc_sdram_get_niu_config(sdram_params);
if (ret)
goto error;
rk3066_dmc_dram_all_config(dram, sdram_params);
debug("SDRAM init OK!\n");
return 0;
error:
debug("SDRAM init failed!\n");
hang();
}
static int rk3066_dmc_setup_sdram(struct udevice *dev)
{
struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
struct rk3066_dmc_sdram_params *params = dev_get_plat(dev);
return rk3066_dmc_sdram_init(priv, params);
}
static int rk3066_dmc_conv_of_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev);
struct dtd_rockchip_rk3066_dmc *of_plat = &plat->of_plat;
int ret;
memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
sizeof(plat->pctl_timing));
memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
sizeof(plat->phy_timing));
memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
/* RK3066 supports dual-channel, set default channel num to 2. */
plat->num_channels = 1;
ret = regmap_init_mem_plat(dev, of_plat->reg,
ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
if (ret)
return ret;
return 0;
#else
return -EINVAL;
#endif
}
static int rk3066_dmc_probe(struct udevice *dev)
{
struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
if (IS_ENABLED(CONFIG_TPL_BUILD)) {
struct rk3066_dmc_sdram_params *plat = dev_get_plat(dev);
struct regmap *map;
struct udevice *dev_clk;
int ret;
ret = rk3066_dmc_conv_of_plat(dev);
if (ret)
return ret;
map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
if (IS_ERR(map))
return PTR_ERR(map);
priv->chan[0].msch = regmap_get_range(map, 0);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->chan[0].pctl = regmap_get_range(plat->map, 0);
priv->chan[0].publ = regmap_get_range(plat->map, 1);
ret = rockchip_get_clk(&dev_clk);
if (ret)
return ret;
priv->ddr_clk.id = CLK_DDR;
ret = clk_request(dev_clk, &priv->ddr_clk);
if (ret)
return ret;
priv->cru = rockchip_get_cru();
if (IS_ERR(priv->cru))
return PTR_ERR(priv->cru);
ret = rk3066_dmc_setup_sdram(dev);
if (ret)
return ret;
} else {
priv->info.base = CONFIG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]);
}
return 0;
}
static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info)
{
struct rk3066_dmc_dram_info *priv = dev_get_priv(dev);
*info = priv->info;
return 0;
}
static struct ram_ops rk3066_dmc_ops = {
.get_info = rk3066_dmc_get_info,
};
static const struct udevice_id rk3066_dmc_ids[] = {
{ .compatible = "rockchip,rk3066-dmc" },
{ }
};
U_BOOT_DRIVER(rockchip_rk3066_dmc) = {
.name = "rockchip_rk3066_dmc",
.id = UCLASS_RAM,
.ops = &rk3066_dmc_ops,
.probe = rk3066_dmc_probe,
.of_match = rk3066_dmc_ids,
.priv_auto = sizeof(struct rk3066_dmc_dram_info),
#if IS_ENABLED(CONFIG_TPL_BUILD)
.plat_auto = sizeof(struct rk3066_dmc_sdram_params),
#endif
};

5
drivers/serial/Kconfig
View File

@@ -762,10 +762,11 @@ config PL01X_SERIAL
config ROCKCHIP_SERIAL
bool "Rockchip on-chip UART support"
depends on DM_SERIAL && SPL_OF_PLATDATA
depends on DM_SERIAL
select SYS_NS16550
help
Select this to enable a debug UART for Rockchip devices when using
CONFIG_SPL_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt).
OF_PLATDATA (i.e. a compiled-in device tree replacemenmt).
This uses the ns16550 driver, converting the platdata from of-platdata
to the ns16550 format.

2
drivers/serial/Makefile
View File

@@ -46,9 +46,7 @@ obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
endif
obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
obj-$(CONFIG_SCIF_CONSOLE) += serial_sh.o

2
drivers/serial/ns16550.c
View File

@@ -624,8 +624,6 @@ U_BOOT_DRIVER(ns16550_serial) = {
#endif
};
DM_DRIVER_ALIAS(ns16550_serial, rockchip_rk3328_uart)
DM_DRIVER_ALIAS(ns16550_serial, rockchip_rk3368_uart)
DM_DRIVER_ALIAS(ns16550_serial, ti_da830_uart)
#endif
#endif /* SERIAL_PRESENT */

38
drivers/serial/serial_rockchip.c
View File

@@ -12,22 +12,20 @@
#include <asm/arch-rockchip/clock.h>
#include <dm/device-internal.h>
#if defined(CONFIG_ROCKCHIP_RK3188)
struct rockchip_uart_plat {
struct dtd_rockchip_rk3188_uart dtplat;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_uart dtplat;
#endif
struct ns16550_plat plat;
};
struct dtd_rockchip_rk3188_uart *dtplat, s_dtplat;
#elif defined(CONFIG_ROCKCHIP_RK3288)
struct rockchip_uart_plat {
struct dtd_rockchip_rk3288_uart dtplat;
struct ns16550_plat plat;
};
struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_uart *dtplat, s_dtplat;
#endif
static int rockchip_serial_probe(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_uart_plat *plat = dev_get_plat(dev);
/* Create some new platform data for the standard driver */
@@ -38,20 +36,13 @@ static int rockchip_serial_probe(struct udevice *dev)
dev_set_plat(dev, &plat->plat);
return ns16550_serial_probe(dev);
#else
return -ENODEV;
#endif
}
U_BOOT_DRIVER(rockchip_rk3188_uart) = {
.name = "rockchip_rk3188_uart",
.id = UCLASS_SERIAL,
.priv_auto = sizeof(struct ns16550),
.plat_auto = sizeof(struct rockchip_uart_plat),
.probe = rockchip_serial_probe,
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER(rockchip_rk3288_uart) = {
.name = "rockchip_rk3288_uart",
U_BOOT_DRIVER(rockchip_uart) = {
.name = "rockchip_uart",
.id = UCLASS_SERIAL,
.priv_auto = sizeof(struct ns16550),
.plat_auto = sizeof(struct rockchip_uart_plat),
@@ -59,3 +50,8 @@ U_BOOT_DRIVER(rockchip_rk3288_uart) = {
.ops = &ns16550_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3066_uart)
DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3188_uart)
DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3288_uart)
DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3328_uart)
DM_DRIVER_ALIAS(rockchip_uart, rockchip_rk3368_uart)

1
drivers/spi/rockchip_sfc.c
View File

@@ -12,6 +12,7 @@
#include <bouncebuf.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/iopoll.h>

28
drivers/timer/dw-apb-timer.c
View File

@@ -8,10 +8,12 @@
#include <common.h>
#include <dm.h>
#include <clk.h>
#include <dt-structs.h>
#include <malloc.h>
#include <reset.h>
#include <timer.h>
#include <dm/device_compat.h>
#include <linux/kconfig.h>
#include <asm/io.h>
#include <asm/arch/timer.h>
@@ -25,6 +27,12 @@ struct dw_apb_timer_priv {
struct reset_ctl_bulk resets;
};
struct dw_apb_timer_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_snps_dw_apb_timer dtplat;
#endif
};
static u64 dw_apb_timer_get_count(struct udevice *dev)
{
struct dw_apb_timer_priv *priv = dev_get_priv(dev);
@@ -43,7 +51,19 @@ static int dw_apb_timer_probe(struct udevice *dev)
struct dw_apb_timer_priv *priv = dev_get_priv(dev);
struct clk clk;
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dw_apb_timer_plat *plat = dev_get_plat(dev);
struct dtd_snps_dw_apb_timer *dtplat = &plat->dtplat;
priv->regs = dtplat->reg[0];
ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk);
if (ret < 0)
return ret;
uc_priv->clock_rate = dtplat->clock_frequency;
#endif
if (CONFIG_IS_ENABLED(OF_REAL)) {
ret = reset_get_bulk(dev, &priv->resets);
if (ret)
dev_warn(dev, "Can't get reset: %d\n", ret);
@@ -57,6 +77,7 @@ static int dw_apb_timer_probe(struct udevice *dev)
uc_priv->clock_rate = clk_get_rate(&clk);
clk_free(&clk);
}
/* init timer */
writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL);
@@ -68,9 +89,11 @@ static int dw_apb_timer_probe(struct udevice *dev)
static int dw_apb_timer_of_to_plat(struct udevice *dev)
{
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct dw_apb_timer_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr(dev);
}
return 0;
}
@@ -91,8 +114,8 @@ static const struct udevice_id dw_apb_timer_ids[] = {
{}
};
U_BOOT_DRIVER(dw_apb_timer) = {
.name = "dw_apb_timer",
U_BOOT_DRIVER(snps_dw_apb_timer) = {
.name = "snps_dw_apb_timer",
.id = UCLASS_TIMER,
.ops = &dw_apb_timer_ops,
.probe = dw_apb_timer_probe,
@@ -100,4 +123,5 @@ U_BOOT_DRIVER(dw_apb_timer) = {
.of_to_plat = dw_apb_timer_of_to_plat,
.remove = dw_apb_timer_remove,
.priv_auto = sizeof(struct dw_apb_timer_priv),
.plat_auto = sizeof(struct dw_apb_timer_plat),
};

1
drivers/video/rockchip/rk3288_mipi.c
View File

@@ -174,6 +174,7 @@ static const struct dm_display_ops rk_mipi_dsi_ops = {
};
static const struct udevice_id rk_mipi_dsi_ids[] = {
{ .compatible = "rockchip,rk3288-mipi-dsi" },
{ .compatible = "rockchip,rk3288_mipi_dsi" },
{ }
};

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