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clk: uniphier: add EMMC clock for LD11, LD20, and PXs3

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I also added comments for NAND clocks.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
2019-07-10 20:07:35 +09:00
parent b521ea3958
commit 9a2f0e5ccd
1 changed files with 8 additions and 6 deletions
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14
drivers/clk/uniphier/clk-uniphier-sys.c
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@@ -18,8 +18,8 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8) ||\
defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
UNIPHIER_LD4_SYS_CLK_NAND(2),
UNIPHIER_CLK_RATE(3, 200000000),
UNIPHIER_LD4_SYS_CLK_NAND(2), /* nand */
UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */
UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */
@@ -35,8 +35,9 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
UNIPHIER_LD11_SYS_CLK_NAND(2),
UNIPHIER_CLK_RATE(3, 200000000),
UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */
UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */
UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */
UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */
@@ -48,8 +49,9 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
#if defined(CONFIG_ARCH_UNIPHIER_PXS3)
UNIPHIER_LD11_SYS_CLK_NAND(2),
UNIPHIER_CLK_RATE(3, 200000000),
UNIPHIER_LD11_SYS_CLK_NAND(2), /* nand */
UNIPHIER_CLK_RATE(3, 200000000), /* nand-4x */
UNIPHIER_CLK_GATE_SIMPLE(4, 0x210c, 2), /* emmc */
UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */
UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */
UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */