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powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@@ -68,6 +68,7 @@ static const char *serdes_prtcl_str[] = {
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[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
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[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
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[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
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[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
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[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
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[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
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[SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
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[XAUI_FM1] = "XAUI_FM1",
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[XAUI_FM1] = "XAUI_FM1",
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[XAUI_FM2] = "XAUI_FM2",
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[XAUI_FM2] = "XAUI_FM2",
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[AURORA] = "DEBUG",
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[AURORA] = "DEBUG",
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@@ -658,6 +659,7 @@ void fsl_serdes_init(void)
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case SGMII_FM2_DTSEC2:
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case SGMII_FM2_DTSEC2:
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case SGMII_FM2_DTSEC3:
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case SGMII_FM2_DTSEC3:
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case SGMII_FM2_DTSEC4:
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case SGMII_FM2_DTSEC4:
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case SGMII_FM2_DTSEC5:
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case XAUI_FM1:
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case XAUI_FM1:
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case XAUI_FM2:
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case XAUI_FM2:
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case SRIO1:
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case SRIO1:
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@@ -717,6 +719,10 @@ void fsl_serdes_init(void)
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
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FSL_CORENET_DEVDISR2_DTSEC2_4;
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FSL_CORENET_DEVDISR2_DTSEC2_4;
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break;
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break;
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case SGMII_FM2_DTSEC5:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
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FSL_CORENET_DEVDISR2_DTSEC2_5;
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break;
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case XAUI_FM1:
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case XAUI_FM1:
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
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serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
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FSL_CORENET_DEVDISR2_10GEC1;
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FSL_CORENET_DEVDISR2_10GEC1;
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@@ -41,6 +41,7 @@ enum srds_prtcl {
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SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC4,
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SGMII_FM2_DTSEC4,
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SGMII_FM2_DTSEC5,
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SGMII_TSEC1,
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SGMII_TSEC1,
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SGMII_TSEC2,
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SGMII_TSEC2,
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SGMII_TSEC3,
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SGMII_TSEC3,
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@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
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#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
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#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
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#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
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#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
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#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
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#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
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#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
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#define FSL_CORENET_NUM_DEVDISR 2
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#define FSL_CORENET_NUM_DEVDISR 2
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u8 res7[8];
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u8 res7[8];
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u32 powmgtcsr; /* Power management status & control */
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u32 powmgtcsr; /* Power management status & control */
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@@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = {
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
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FM_DTSEC_INFO_INITIALIZER(2, 4),
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FM_DTSEC_INFO_INITIALIZER(2, 4),
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#endif
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#endif
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#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
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FM_DTSEC_INFO_INITIALIZER(2, 5),
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#endif
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#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
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#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
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FM_TGEC_INFO_INITIALIZER(1, 1),
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FM_TGEC_INFO_INITIALIZER(1, 1),
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#endif
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#endif
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@@ -35,6 +35,7 @@ enum fm_port {
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FM2_DTSEC2,
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FM2_DTSEC2,
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FM2_DTSEC3,
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FM2_DTSEC3,
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FM2_DTSEC4,
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FM2_DTSEC4,
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FM2_DTSEC5,
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FM2_10GEC1,
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FM2_10GEC1,
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NUM_FM_PORTS,
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NUM_FM_PORTS,
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};
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};
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