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powerpc/85xx: add support for FM2 DTSEC5

Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Timur Tabi
2012-08-14 06:47:21 +00:00
committed by Andy Fleming
parent a2af6a7a84
commit 99abf7ded3
5 changed files with 12 additions and 0 deletions

View File

@@ -68,6 +68,7 @@ static const char *serdes_prtcl_str[] = {
[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
[SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
[XAUI_FM1] = "XAUI_FM1", [XAUI_FM1] = "XAUI_FM1",
[XAUI_FM2] = "XAUI_FM2", [XAUI_FM2] = "XAUI_FM2",
[AURORA] = "DEBUG", [AURORA] = "DEBUG",
@@ -658,6 +659,7 @@ void fsl_serdes_init(void)
case SGMII_FM2_DTSEC2: case SGMII_FM2_DTSEC2:
case SGMII_FM2_DTSEC3: case SGMII_FM2_DTSEC3:
case SGMII_FM2_DTSEC4: case SGMII_FM2_DTSEC4:
case SGMII_FM2_DTSEC5:
case XAUI_FM1: case XAUI_FM1:
case XAUI_FM2: case XAUI_FM2:
case SRIO1: case SRIO1:
@@ -717,6 +719,10 @@ void fsl_serdes_init(void)
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 | serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
FSL_CORENET_DEVDISR2_DTSEC2_4; FSL_CORENET_DEVDISR2_DTSEC2_4;
break; break;
case SGMII_FM2_DTSEC5:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
FSL_CORENET_DEVDISR2_DTSEC2_5;
break;
case XAUI_FM1: case XAUI_FM1:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 | serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
FSL_CORENET_DEVDISR2_10GEC1; FSL_CORENET_DEVDISR2_10GEC1;

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@@ -41,6 +41,7 @@ enum srds_prtcl {
SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4, SGMII_FM2_DTSEC4,
SGMII_FM2_DTSEC5,
SGMII_TSEC1, SGMII_TSEC1,
SGMII_TSEC2, SGMII_TSEC2,
SGMII_TSEC3, SGMII_TSEC3,

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@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
#define FSL_CORENET_NUM_DEVDISR 2 #define FSL_CORENET_NUM_DEVDISR 2
u8 res7[8]; u8 res7[8];
u32 powmgtcsr; /* Power management status & control */ u32 powmgtcsr; /* Power management status & control */

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@@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4) #if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4), FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif #endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(2, 5),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1) #if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1), FM_TGEC_INFO_INITIALIZER(1, 1),
#endif #endif

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@@ -35,6 +35,7 @@ enum fm_port {
FM2_DTSEC2, FM2_DTSEC2,
FM2_DTSEC3, FM2_DTSEC3,
FM2_DTSEC4, FM2_DTSEC4,
FM2_DTSEC5,
FM2_10GEC1, FM2_10GEC1,
NUM_FM_PORTS, NUM_FM_PORTS,
}; };