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rockchip: rk3036: change ddr frequency to 400M

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emac may use dpll as clock parent, and it request the clock frequency
multiples of 50, so change ddr frequency to 400M.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Lin Huang
2016-02-17 15:55:05 +08:00
committed by Simon Glass
parent deff6fb3a7
commit 99aaa93075
1 changed files with 1 additions and 1 deletions
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arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
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@@ -37,7 +37,7 @@ struct rk3036_sdram_priv {
/* use integer mode, 396MHz dpll setting /* use integer mode, 396MHz dpll setting
* refdiv, fbdiv, postdiv1, postdiv2 * refdiv, fbdiv, postdiv1, postdiv2
*/ */
const struct pll_div dpll_init_cfg = {1, 66, 4, 1}; const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
/* 396Mhz ddr timing */ /* 396Mhz ddr timing */
const struct rk3036_ddr_timing ddr_timing = {0x18c, const struct rk3036_ddr_timing ddr_timing = {0x18c,