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net: tsec: fsl_mdio: Fix several cosmetic issues
Clean up the tsec and fsl_mdio driver codes a little bit, by: - Fix misuse of tab and space here and there - Use correct multi-line comment format - Replace license identifier to GPL-2.0+ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Bin Meng
committed by
Joe Hershberger
Joe Hershberger
parent
9ccb309651
commit
9872b736f9
@@ -3,15 +3,12 @@
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*
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* Driver for the Motorola Triple Speed Ethernet Controller
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
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* (C) Copyright 2003, Motorola, Inc.
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* maintained by Xianghua Xiao (x.xiao@motorola.com)
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* author Andy Fleming
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __TSEC_H
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@@ -67,11 +64,11 @@
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x.mii_devname = DEFAULT_MII_NAME;\
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}
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#define MAC_ADDR_LEN 6
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#define MAC_ADDR_LEN 6
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/* #define TSEC_TIMEOUT 1000000 */
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#define TSEC_TIMEOUT 1000
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#define TOUT_LOOP 1000000
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#define TSEC_TIMEOUT 1000
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#define TOUT_LOOP 1000000
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/* TBI register addresses */
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#define TBI_CR 0x00
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@@ -83,8 +80,8 @@
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/* TBI MDIO register bit fields*/
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#define TBICON_CLK_SELECT 0x0020
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_HALF_DUPLEX 0x0040
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#define TBIANA_FULL_DUPLEX 0x0020
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#define TBICR_PHY_RESET 0x8000
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@@ -93,13 +90,12 @@
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#define TBICR_FULL_DUPLEX 0x0100
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#define TBICR_SPEED1_SET 0x0040
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/* MAC register bits */
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#define MACCFG1_SOFT_RESET 0x80000000
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#define MACCFG1_RESET_RX_MC 0x00080000
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#define MACCFG1_RESET_TX_MC 0x00040000
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#define MACCFG1_RESET_RX_FUN 0x00020000
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#define MACCFG1_RESET_TX_FUN 0x00010000
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#define MACCFG1_RESET_TX_FUN 0x00010000
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#define MACCFG1_LOOPBACK 0x00000100
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#define MACCFG1_RX_FLOW 0x00000020
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#define MACCFG1_TX_FLOW 0x00000010
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@@ -122,7 +118,7 @@
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#define ECNTRL_SGMII_MODE 0x00000002
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#ifndef CONFIG_SYS_TBIPA_VALUE
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#define CONFIG_SYS_TBIPA_VALUE 0x1f
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# define CONFIG_SYS_TBIPA_VALUE 0x1f
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#endif
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#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
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@@ -137,7 +133,6 @@
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#define TSTAT_CLEAR_THALT 0x80000000
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#define RSTAT_CLEAR_RHALT 0x00800000
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#define IEVENT_INIT_CLEAR 0xffffffff
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#define IEVENT_BABR 0x80000000
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#define IEVENT_RXC 0x40000000
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@@ -164,11 +159,9 @@
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#define IMASK_TXFEN 0x00100000
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#define IMASK_RXFEN0 0x00000080
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/* Default Attribute fields */
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#define ATTR_INIT_SETTINGS 0x000000c0
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#define ATTRELI_INIT_SETTINGS 0x00000000
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#define ATTR_INIT_SETTINGS 0x000000c0
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#define ATTRELI_INIT_SETTINGS 0x00000000
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/* TxBD status field bits */
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#define TXBD_READY 0x8000
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@@ -181,7 +174,7 @@
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#define TXBD_HUGEFRAME 0x0080
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#define TXBD_LATECOLLISION 0x0080
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#define TXBD_RETRYLIMIT 0x0040
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#define TXBD_RETRYCOUNTMASK 0x003c
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#define TXBD_RETRYCOUNTMASK 0x003c
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#define TXBD_UNDERRUN 0x0002
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#define TXBD_STATS 0x03ff
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@@ -204,15 +197,15 @@
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#define RXBD_STATS 0x003f
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struct txbd8 {
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer length */
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uint32_t bufptr; /* Buffer Pointer */
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer length */
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uint32_t bufptr; /* Buffer Pointer */
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};
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struct rxbd8 {
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer Length */
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uint32_t bufptr; /* Buffer Pointer */
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uint16_t status; /* Status Fields */
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uint16_t length; /* Buffer Length */
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uint32_t bufptr; /* Buffer Pointer */
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};
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struct tsec_rmon_mib {
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@@ -336,15 +329,15 @@ struct tsec {
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u32 rbdlen; /* RxBD Data Length */
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u32 res310[4];
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u32 res320;
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u32 crbptr; /* Current Receive Buffer Pointer */
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u32 crbptr; /* Current Receive Buffer Pointer */
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u32 res328[6];
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u32 mrblr; /* Maximum Receive Buffer Length */
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u32 mrblr; /* Maximum Receive Buffer Length */
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u32 res344[16];
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u32 rbptr; /* RxBD Pointer */
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u32 rbptr; /* RxBD Pointer */
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u32 res388[30];
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/* (0x2_n400) */
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u32 res400;
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u32 rbase; /* RxBD Base Address */
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u32 rbase; /* RxBD Base Address */
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u32 res408[62];
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/* MAC Registers (0x2_n500) */
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@@ -388,7 +381,7 @@ struct tsec {
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u32 resc00[256];
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};
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#define TSEC_GIGABIT (1 << 0)
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#define TSEC_GIGABIT (1 << 0)
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/* These flags currently only have meaning if we're using the eTSEC */
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#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
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