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x86: Set up a shared syscon numbering schema

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Each system controller can have a number to identify it. It can then be
accessed using syscon_get_by_driver_data(). Put this in a shared header
file and update the only current user.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
2016-01-17 16:11:58 -07:00
committed by Bin Meng
parent 67292e4c27
commit 98655f3a8d
4 changed files with 16 additions and 4 deletions
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3
arch/x86/cpu/ivybridge/early_me.c
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@@ -10,6 +10,7 @@
#include <dm.h> #include <dm.h>
#include <errno.h> #include <errno.h>
#include <asm/pci.h> #include <asm/pci.h>
#include <asm/cpu.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/arch/me.h> #include <asm/arch/me.h>
#include <asm/arch/pch.h> #include <asm/arch/pch.h>
@@ -189,7 +190,7 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
} }
static const struct udevice_id ivybridge_syscon_ids[] = { static const struct udevice_id ivybridge_syscon_ids[] = {
{ .compatible = "intel,me", }, { .compatible = "intel,me", .data = X86_SYSCON_ME },
{ } { }
}; };

6
arch/x86/cpu/ivybridge/sdram.c
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@@ -18,6 +18,8 @@
#include <rtc.h> #include <rtc.h>
#include <spi.h> #include <spi.h>
#include <spi_flash.h> #include <spi_flash.h>
#include <syscon.h>
#include <asm/cpu.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/global_data.h> #include <asm/global_data.h>
@@ -739,11 +741,9 @@ int dram_init(void)
return ret; return ret;
if (!dev) if (!dev)
return -ENODEV; return -ENODEV;
ret = uclass_first_device(UCLASS_SYSCON, &me_dev); ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
if (ret) if (ret)
return ret; return ret;
if (!me_dev)
return -ENODEV;
debug("Boot mode %d\n", gd->arch.pei_boot_mode); debug("Boot mode %d\n", gd->arch.pei_boot_mode);
debug("mrc_input %p\n", pei_data.mrc_input); debug("mrc_input %p\n", pei_data.mrc_input);
pei_data.boot_mode = gd->arch.pei_boot_mode; pei_data.boot_mode = gd->arch.pei_boot_mode;

9
arch/x86/include/asm/cpu.h
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@@ -45,6 +45,15 @@ enum {
GDT_BASE_HIGH_MASK = 0xf, GDT_BASE_HIGH_MASK = 0xf,
}; };
/*
* System controllers in an x86 system. We mostly need to just find these and
* use them on PCI. At some point these might have their own uclass.
*/
enum {
X86_NONE,
X86_SYSCON_ME, /* Intel Management Engine */
};
struct cpuid_result { struct cpuid_result {
uint32_t eax; uint32_t eax;
uint32_t ebx; uint32_t ebx;

2
configs/chromebox_panther_defconfig
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@@ -16,6 +16,8 @@ CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_TPM=y CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y CONFIG_CMD_TPM_TEST=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CMD_CROS_EC=y CONFIG_CMD_CROS_EC=y
CONFIG_CROS_EC=y CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_LPC=y