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ARM: DRA7xx: clocks: Update PLL values

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Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
This commit is contained in:
Lokesh Vutla
2013-05-30 03:19:38 +00:00
committed by Tom Rini
parent 7f36c88f64
commit 97405d843e
7 changed files with 73 additions and 46 deletions
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2
arch/arm/include/asm/arch-omap4/clock.h
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@@ -76,7 +76,7 @@
#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT 0