mirror of
https://xff.cz/git/u-boot/
synced 2025-09-02 09:12:08 +02:00
MX5:MX53: add initial support for MX53EVK board
Add initial support for MX53EVK board support. FEC, SD/MMC, UART, I2C, have been supported. Signed-off-by: Jason Liu <r64343@freescale.com>
This commit is contained in:
Liu Hui-R64343
committed by
Albert Aribaud
Albert Aribaud
parent
3382fd48f2
commit
94391fbcee
@@ -562,6 +562,10 @@ Stefano Babic <sbabic@denx.de>
|
|||||||
mx51evk i.MX51
|
mx51evk i.MX51
|
||||||
vision2 i.MX51
|
vision2 i.MX51
|
||||||
|
|
||||||
|
Jason Liu <r64343@freescale.com>
|
||||||
|
|
||||||
|
mx53evk i.MX53
|
||||||
|
|
||||||
Enric Balletbo i Serra <eballetbo@iseebcn.com>
|
Enric Balletbo i Serra <eballetbo@iseebcn.com>
|
||||||
|
|
||||||
igep0020 ARM ARMV7 (OMAP3xx SoC)
|
igep0020 ARM ARMV7 (OMAP3xx SoC)
|
||||||
|
|||||||
48
board/freescale/mx53evk/Makefile
Normal file
48
board/freescale/mx53evk/Makefile
Normal file
@@ -0,0 +1,48 @@
|
|||||||
|
#
|
||||||
|
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||||
|
#
|
||||||
|
# (C) Copyright 2010 Freescale Semiconductor, Inc.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
|
LIB = $(obj)lib$(BOARD).o
|
||||||
|
|
||||||
|
COBJS := mx53evk.o
|
||||||
|
|
||||||
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
|
||||||
|
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||||
|
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(SOBJS) $(OBJS)
|
||||||
|
|
||||||
|
distclean: clean
|
||||||
|
rm -f $(LIB) core *.bak .depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
# defines $(obj).depend target
|
||||||
|
include $(SRCTREE)/rules.mk
|
||||||
|
|
||||||
|
sinclude $(obj).depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
24
board/freescale/mx53evk/config.mk
Normal file
24
board/freescale/mx53evk/config.mk
Normal file
@@ -0,0 +1,24 @@
|
|||||||
|
#
|
||||||
|
# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
|
||||||
|
ALL += $(obj)u-boot.imx
|
||||||
112
board/freescale/mx53evk/imximage.cfg
Normal file
112
board/freescale/mx53evk/imximage.cfg
Normal file
@@ -0,0 +1,112 @@
|
|||||||
|
#
|
||||||
|
# (C Copyright 2009
|
||||||
|
# Stefano Babic DENX Software Engineering sbabic@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not write to the Free Software
|
||||||
|
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||||
|
# MA 02110-1301 USA
|
||||||
|
#
|
||||||
|
# Refer docs/README.imxmage for more details about how-to configure
|
||||||
|
# and create imximage boot image
|
||||||
|
#
|
||||||
|
# The syntax is taken as close as possible with the kwbimage
|
||||||
|
|
||||||
|
# image version
|
||||||
|
|
||||||
|
IMAGE_VERSION 2
|
||||||
|
|
||||||
|
# Boot Device : one of
|
||||||
|
# spi, sd (the board has no nand neither onenand)
|
||||||
|
|
||||||
|
BOOT_FROM sd
|
||||||
|
|
||||||
|
# Device Configuration Data (DCD)
|
||||||
|
#
|
||||||
|
# Each entry must have the format:
|
||||||
|
# Addr-type Address Value
|
||||||
|
#
|
||||||
|
# where:
|
||||||
|
# Addr-type register length (1,2 or 4 bytes)
|
||||||
|
# Address absolute address of the register
|
||||||
|
# value value to be stored in the register
|
||||||
|
|
||||||
|
# Setting IOMUXC
|
||||||
|
DATA 4 0x53fa8554 0x00200000
|
||||||
|
DATA 4 0x53fa8560 0x00200000
|
||||||
|
DATA 4 0x53fa8594 0x00200000
|
||||||
|
DATA 4 0x53fa8584 0x00200000
|
||||||
|
DATA 4 0x53fa8558 0x00200040
|
||||||
|
DATA 4 0x53fa8568 0x00200040
|
||||||
|
DATA 4 0x53fa8590 0x00200040
|
||||||
|
DATA 4 0x53fa857c 0x00200040
|
||||||
|
DATA 4 0x53fa8564 0x00200040
|
||||||
|
DATA 4 0x53fa8580 0x00200040
|
||||||
|
DATA 4 0x53fa8570 0x00200000
|
||||||
|
DATA 4 0x53fa8578 0x00200000
|
||||||
|
DATA 4 0x53fa872c 0x00200000
|
||||||
|
DATA 4 0x53fa8728 0x00200000
|
||||||
|
DATA 4 0x53fa871c 0x00200000
|
||||||
|
DATA 4 0x53fa8718 0x00200000
|
||||||
|
DATA 4 0x53fa8574 0x00280000
|
||||||
|
DATA 4 0x53fa8588 0x00280000
|
||||||
|
DATA 4 0x53fa86f0 0x00280000
|
||||||
|
DATA 4 0x53fa8720 0x00280000
|
||||||
|
DATA 4 0x53fa86fc 0x00000000
|
||||||
|
DATA 4 0x53fa86f4 0x00000200
|
||||||
|
DATA 4 0x53fa8714 0x00000000
|
||||||
|
DATA 4 0x53fa8724 0x06000000
|
||||||
|
DATA 4 0x63fd9088 0x34333936
|
||||||
|
DATA 4 0x63fd9090 0x49434942
|
||||||
|
DATA 4 0x63fd90F8 0x00000800
|
||||||
|
DATA 4 0x63fd907c 0x01350138
|
||||||
|
DATA 4 0x63fd9080 0x01380139
|
||||||
|
DATA 4 0x63fd9018 0x00001710
|
||||||
|
DATA 4 0x63fd9000 0xc4110000
|
||||||
|
DATA 4 0x63fd900C 0x4d5122d2
|
||||||
|
DATA 4 0x63fd9010 0x92d18a22
|
||||||
|
DATA 4 0x63fd9014 0x00c70092
|
||||||
|
DATA 4 0x63fd902c 0x000026d2
|
||||||
|
DATA 4 0x63fd9030 0x009f000e
|
||||||
|
DATA 4 0x63fd9008 0x12272000
|
||||||
|
DATA 4 0x63fd9004 0x00030012
|
||||||
|
DATA 4 0x63fd901c 0x04008010
|
||||||
|
DATA 4 0x63fd901c 0x00008032
|
||||||
|
DATA 4 0x63fd901c 0x00008033
|
||||||
|
DATA 4 0x63fd901c 0x00008031
|
||||||
|
DATA 4 0x63fd901c 0x0b5280b0
|
||||||
|
DATA 4 0x63fd901c 0x04008010
|
||||||
|
DATA 4 0x63fd901c 0x00008020
|
||||||
|
DATA 4 0x63fd901c 0x00008020
|
||||||
|
DATA 4 0x63fd901c 0x0a528030
|
||||||
|
DATA 4 0x63fd901c 0x03c68031
|
||||||
|
DATA 4 0x63fd901c 0x00448031
|
||||||
|
DATA 4 0x63fd901c 0x04008018
|
||||||
|
DATA 4 0x63fd901c 0x0000803a
|
||||||
|
DATA 4 0x63fd901c 0x0000803b
|
||||||
|
DATA 4 0x63fd901c 0x00008039
|
||||||
|
DATA 4 0x63fd901c 0x0b528138
|
||||||
|
DATA 4 0x63fd901c 0x04008018
|
||||||
|
DATA 4 0x63fd901c 0x00008028
|
||||||
|
DATA 4 0x63fd901c 0x00008028
|
||||||
|
DATA 4 0x63fd901c 0x0a528038
|
||||||
|
DATA 4 0x63fd901c 0x03c68039
|
||||||
|
DATA 4 0x63fd901c 0x00448039
|
||||||
|
DATA 4 0x63fd9020 0x00005800
|
||||||
|
DATA 4 0x63fd9058 0x00033335
|
||||||
|
DATA 4 0x63fd901c 0x00000000
|
||||||
|
DATA 4 0x63fd9040 0x04b80003
|
||||||
|
DATA 4 0x53fa8004 0x00194005
|
||||||
397
board/freescale/mx53evk/mx53evk.c
Normal file
397
board/freescale/mx53evk/mx53evk.c
Normal file
@@ -0,0 +1,397 @@
|
|||||||
|
/*
|
||||||
|
* (C) Copyright 2010 Freescale Semiconductor, Inc.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/arch/imx-regs.h>
|
||||||
|
#include <asm/arch/mx5x_pins.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#include <asm/arch/crm_regs.h>
|
||||||
|
#include <asm/arch/iomux.h>
|
||||||
|
#include <asm/errno.h>
|
||||||
|
#include <netdev.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#include <mmc.h>
|
||||||
|
#include <fsl_esdhc.h>
|
||||||
|
#include <fsl_pmic.h>
|
||||||
|
#include <mxc_gpio.h>
|
||||||
|
#include <mc13892.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
u32 get_board_rev(void)
|
||||||
|
{
|
||||||
|
return get_cpu_rev();
|
||||||
|
}
|
||||||
|
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
/* dram_init must store complete ramsize in gd->ram_size */
|
||||||
|
gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
|
||||||
|
PHYS_SDRAM_1_SIZE);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setup_iomux_uart(void)
|
||||||
|
{
|
||||||
|
/* UART1 RXD */
|
||||||
|
mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
|
||||||
|
PAD_CTL_ODE_OPENDRAIN_ENABLE);
|
||||||
|
mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
|
||||||
|
|
||||||
|
/* UART1 TXD */
|
||||||
|
mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
|
||||||
|
PAD_CTL_ODE_OPENDRAIN_ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setup_i2c(unsigned int port_number)
|
||||||
|
{
|
||||||
|
switch (port_number) {
|
||||||
|
case 0:
|
||||||
|
/* i2c1 SDA */
|
||||||
|
mxc_request_iomux(MX53_PIN_CSI0_D8,
|
||||||
|
IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
|
||||||
|
mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
|
||||||
|
INPUT_CTL_PATH0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
|
||||||
|
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
|
||||||
|
PAD_CTL_ODE_OPENDRAIN_ENABLE);
|
||||||
|
/* i2c1 SCL */
|
||||||
|
mxc_request_iomux(MX53_PIN_CSI0_D9,
|
||||||
|
IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
|
||||||
|
mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
|
||||||
|
INPUT_CTL_PATH0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
|
||||||
|
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
|
||||||
|
PAD_CTL_ODE_OPENDRAIN_ENABLE);
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
/* i2c2 SDA */
|
||||||
|
mxc_request_iomux(MX53_PIN_KEY_ROW3,
|
||||||
|
IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
|
||||||
|
mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
|
||||||
|
INPUT_CTL_PATH0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
|
||||||
|
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
|
||||||
|
PAD_CTL_ODE_OPENDRAIN_ENABLE);
|
||||||
|
|
||||||
|
/* i2c2 SCL */
|
||||||
|
mxc_request_iomux(MX53_PIN_KEY_COL3,
|
||||||
|
IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
|
||||||
|
mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
|
||||||
|
INPUT_CTL_PATH0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
|
||||||
|
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
|
||||||
|
PAD_CTL_ODE_OPENDRAIN_ENABLE);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("Warning: Wrong I2C port number\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void power_init(void)
|
||||||
|
{
|
||||||
|
unsigned int val;
|
||||||
|
|
||||||
|
/* Set VDDA to 1.25V */
|
||||||
|
val = pmic_reg_read(REG_SW_2);
|
||||||
|
val &= ~SWX_OUT_MASK;
|
||||||
|
val |= SWX_OUT_1_25;
|
||||||
|
pmic_reg_write(REG_SW_2, val);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Need increase VCC and VDDA to 1.3V
|
||||||
|
* according to MX53 IC TO2 datasheet.
|
||||||
|
*/
|
||||||
|
if (is_soc_rev(CHIP_REV_2_0) == 0) {
|
||||||
|
/* Set VCC to 1.3V for TO2 */
|
||||||
|
val = pmic_reg_read(REG_SW_1);
|
||||||
|
val &= ~SWX_OUT_MASK;
|
||||||
|
val |= SWX_OUT_1_30;
|
||||||
|
pmic_reg_write(REG_SW_1, val);
|
||||||
|
|
||||||
|
/* Set VDDA to 1.3V for TO2 */
|
||||||
|
val = pmic_reg_read(REG_SW_2);
|
||||||
|
val &= ~SWX_OUT_MASK;
|
||||||
|
val |= SWX_OUT_1_30;
|
||||||
|
pmic_reg_write(REG_SW_2, val);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setup_iomux_fec(void)
|
||||||
|
{
|
||||||
|
/*FEC_MDIO*/
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
|
||||||
|
mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
|
||||||
|
|
||||||
|
/*FEC_MDC*/
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
|
||||||
|
|
||||||
|
/* FEC RXD1 */
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
|
||||||
|
|
||||||
|
/* FEC RXD0 */
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
|
||||||
|
|
||||||
|
/* FEC TXD1 */
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
|
||||||
|
|
||||||
|
/* FEC TXD0 */
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
|
||||||
|
|
||||||
|
/* FEC TX_EN */
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
|
||||||
|
|
||||||
|
/* FEC TX_CLK */
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
|
||||||
|
|
||||||
|
/* FEC RX_ER */
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
|
||||||
|
|
||||||
|
/* FEC CRS */
|
||||||
|
mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_FSL_ESDHC
|
||||||
|
struct fsl_esdhc_cfg esdhc_cfg[2] = {
|
||||||
|
{MMC_SDHC1_BASE_ADDR, 1},
|
||||||
|
{MMC_SDHC3_BASE_ADDR, 1},
|
||||||
|
};
|
||||||
|
|
||||||
|
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
|
||||||
|
{
|
||||||
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||||
|
|
||||||
|
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
|
||||||
|
*cd = mxc_gpio_get(77); /*GPIO3_13*/
|
||||||
|
else
|
||||||
|
*cd = mxc_gpio_get(75); /*GPIO3_11*/
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_mmc_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
u32 index;
|
||||||
|
s32 status = 0;
|
||||||
|
|
||||||
|
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
|
||||||
|
switch (index) {
|
||||||
|
case 0:
|
||||||
|
mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_request_iomux(MX53_PIN_SD1_DATA0,
|
||||||
|
IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_request_iomux(MX53_PIN_SD1_DATA1,
|
||||||
|
IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_request_iomux(MX53_PIN_SD1_DATA2,
|
||||||
|
IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_request_iomux(MX53_PIN_SD1_DATA3,
|
||||||
|
IOMUX_CONFIG_ALT0);
|
||||||
|
mxc_request_iomux(MX53_PIN_EIM_DA13,
|
||||||
|
IOMUX_CONFIG_ALT1);
|
||||||
|
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||||
|
PAD_CTL_DRV_HIGH);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_RESET_B,
|
||||||
|
IOMUX_CONFIG_ALT2);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_IORDY,
|
||||||
|
IOMUX_CONFIG_ALT2);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_DATA8,
|
||||||
|
IOMUX_CONFIG_ALT4);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_DATA9,
|
||||||
|
IOMUX_CONFIG_ALT4);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_DATA10,
|
||||||
|
IOMUX_CONFIG_ALT4);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_DATA11,
|
||||||
|
IOMUX_CONFIG_ALT4);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_DATA0,
|
||||||
|
IOMUX_CONFIG_ALT4);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_DATA1,
|
||||||
|
IOMUX_CONFIG_ALT4);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_DATA2,
|
||||||
|
IOMUX_CONFIG_ALT4);
|
||||||
|
mxc_request_iomux(MX53_PIN_ATA_DATA3,
|
||||||
|
IOMUX_CONFIG_ALT4);
|
||||||
|
mxc_request_iomux(MX53_PIN_EIM_DA11,
|
||||||
|
IOMUX_CONFIG_ALT1);
|
||||||
|
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||||
|
PAD_CTL_DRV_HIGH);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
|
||||||
|
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
|
||||||
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
|
||||||
|
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("Warning: you configured more ESDHC controller"
|
||||||
|
"(%d) as supported by the board(2)\n",
|
||||||
|
CONFIG_SYS_FSL_ESDHC_NUM);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
setup_iomux_uart();
|
||||||
|
setup_iomux_fec();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
|
||||||
|
/* address of boot parameters */
|
||||||
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_late_init(void)
|
||||||
|
{
|
||||||
|
setup_i2c(1);
|
||||||
|
power_init();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
u32 cause;
|
||||||
|
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||||
|
|
||||||
|
puts("Board: MX53EVK [");
|
||||||
|
|
||||||
|
cause = src_regs->srsr;
|
||||||
|
switch (cause) {
|
||||||
|
case 0x0001:
|
||||||
|
printf("POR");
|
||||||
|
break;
|
||||||
|
case 0x0009:
|
||||||
|
printf("RST");
|
||||||
|
break;
|
||||||
|
case 0x0010:
|
||||||
|
case 0x0011:
|
||||||
|
printf("WDOG");
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("unknown");
|
||||||
|
}
|
||||||
|
printf("]\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
@@ -106,6 +106,7 @@ omap5912osk arm arm926ejs - ti
|
|||||||
edminiv2 arm arm926ejs - LaCie orion5x
|
edminiv2 arm arm926ejs - LaCie orion5x
|
||||||
ca9x4_ct_vxp arm armv7 vexpress armltd
|
ca9x4_ct_vxp arm armv7 vexpress armltd
|
||||||
mx51evk arm armv7 mx51evk freescale mx5
|
mx51evk arm armv7 mx51evk freescale mx5
|
||||||
|
mx53evk arm armv7 mx53evk freescale mx5
|
||||||
vision2 arm armv7 vision2 ttcontrol mx5
|
vision2 arm armv7 vision2 ttcontrol mx5
|
||||||
omap3_overo arm armv7 overo - omap3
|
omap3_overo arm armv7 overo - omap3
|
||||||
omap3_pandora arm armv7 pandora - omap3
|
omap3_pandora arm armv7 pandora - omap3
|
||||||
|
|||||||
193
include/configs/mx53evk.h
Normal file
193
include/configs/mx53evk.h
Normal file
@@ -0,0 +1,193 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2010 Freescale Semiconductor, Inc.
|
||||||
|
*
|
||||||
|
* Configuration settings for the MX53-EVK Freescale board.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
#define CONFIG_MX53
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MX5_HCLK 24000000
|
||||||
|
#define CONFIG_SYS_MX5_CLK32 32768
|
||||||
|
#define CONFIG_DISPLAY_CPUINFO
|
||||||
|
#define CONFIG_DISPLAY_BOARDINFO
|
||||||
|
|
||||||
|
#define CONFIG_L2_OFF
|
||||||
|
|
||||||
|
#include <asm/arch/imx-regs.h>
|
||||||
|
|
||||||
|
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||||
|
#define CONFIG_REVISION_TAG 1
|
||||||
|
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||||
|
#define CONFIG_INITRD_TAG 1
|
||||||
|
|
||||||
|
/* Size of malloc() pool */
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
#define BOARD_LATE_INIT
|
||||||
|
#define CONFIG_MXC_GPIO
|
||||||
|
|
||||||
|
#define CONFIG_MXC_UART
|
||||||
|
#define CONFIG_SYS_MX53_UART1
|
||||||
|
|
||||||
|
/* I2C Configs */
|
||||||
|
#define CONFIG_CMD_I2C 1
|
||||||
|
#define CONFIG_HARD_I2C 1
|
||||||
|
#define CONFIG_I2C_MXC 1
|
||||||
|
#define CONFIG_SYS_I2C_MX53_PORT2 1
|
||||||
|
#define CONFIG_SYS_I2C_SPEED 100000
|
||||||
|
#define CONFIG_SYS_I2C_SLAVE 0xfe
|
||||||
|
|
||||||
|
/* PMIC Configs */
|
||||||
|
#define CONFIG_FSL_PMIC
|
||||||
|
#define CONFIG_FSL_PMIC_I2C
|
||||||
|
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
|
||||||
|
|
||||||
|
/* MMC Configs */
|
||||||
|
#define CONFIG_FSL_ESDHC
|
||||||
|
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||||
|
#define CONFIG_SYS_FSL_ESDHC_NUM 2
|
||||||
|
|
||||||
|
#define CONFIG_MMC
|
||||||
|
#define CONFIG_CMD_MMC
|
||||||
|
#define CONFIG_GENERIC_MMC
|
||||||
|
#define CONFIG_CMD_FAT
|
||||||
|
#define CONFIG_DOS_PARTITION
|
||||||
|
|
||||||
|
/* Eth Configs */
|
||||||
|
#define CONFIG_HAS_ETH1
|
||||||
|
#define CONFIG_NET_MULTI
|
||||||
|
#define CONFIG_MII
|
||||||
|
#define CONFIG_DISCOVER_PHY
|
||||||
|
|
||||||
|
#define CONFIG_FEC_MXC
|
||||||
|
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||||
|
#define CONFIG_FEC_MXC_PHYADDR 0x1F
|
||||||
|
|
||||||
|
#define CONFIG_CMD_PING
|
||||||
|
#define CONFIG_CMD_DHCP
|
||||||
|
#define CONFIG_CMD_MII
|
||||||
|
#define CONFIG_CMD_NET
|
||||||
|
|
||||||
|
/* allow to overwrite serial and ethaddr */
|
||||||
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
#define CONFIG_CONS_INDEX 1
|
||||||
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
|
||||||
|
|
||||||
|
/* Command definition */
|
||||||
|
#include <config_cmd_default.h>
|
||||||
|
|
||||||
|
#undef CONFIG_CMD_IMLS
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 3
|
||||||
|
|
||||||
|
#define CONFIG_PRIME "FEC0"
|
||||||
|
|
||||||
|
#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
|
||||||
|
#define CONFIG_SYS_TEXT_BASE 0x77800000
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"script=boot.scr\0" \
|
||||||
|
"uimage=uImage\0" \
|
||||||
|
"mmcdev=0\0" \
|
||||||
|
"mmcpart=2\0" \
|
||||||
|
"mmcroot=/dev/mmcblk0p3 rw\0" \
|
||||||
|
"mmcrootfstype=ext3 rootwait\0" \
|
||||||
|
"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
|
||||||
|
"root=${mmcroot} " \
|
||||||
|
"rootfstype=${mmcrootfstype}\0" \
|
||||||
|
"loadbootscript=" \
|
||||||
|
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||||
|
"bootscript=echo Running bootscript from mmc ...; " \
|
||||||
|
"source\0" \
|
||||||
|
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||||
|
"mmcboot=echo Booting from mmc ...; " \
|
||||||
|
"run mmcargs; " \
|
||||||
|
"bootm\0" \
|
||||||
|
"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
|
||||||
|
"root=/dev/nfs " \
|
||||||
|
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||||
|
"netboot=echo Booting from net ...; " \
|
||||||
|
"run netargs; " \
|
||||||
|
"dhcp ${uimage}; bootm\0" \
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND \
|
||||||
|
"if mmc rescan ${mmcdev}; then " \
|
||||||
|
"if run loadbootscript; then " \
|
||||||
|
"run bootscript; " \
|
||||||
|
"else " \
|
||||||
|
"if run loaduimage; then " \
|
||||||
|
"run mmcboot; " \
|
||||||
|
"else run netboot; " \
|
||||||
|
"fi; " \
|
||||||
|
"fi; " \
|
||||||
|
"else run netboot; fi"
|
||||||
|
|
||||||
|
#define CONFIG_ARP_TIMEOUT 200UL
|
||||||
|
|
||||||
|
/* Miscellaneous configurable options */
|
||||||
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||||
|
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||||
|
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||||
|
#define CONFIG_SYS_PROMPT "MX53EVK U-Boot > "
|
||||||
|
#define CONFIG_AUTO_COMPLETE
|
||||||
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
|
||||||
|
/* Print Buffer Size */
|
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||||
|
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START 0x70000000
|
||||||
|
#define CONFIG_SYS_MEMTEST_END 0x10000
|
||||||
|
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||||
|
|
||||||
|
#define CONFIG_SYS_HZ 1000
|
||||||
|
#define CONFIG_CMDLINE_EDITING
|
||||||
|
|
||||||
|
/* Stack sizes */
|
||||||
|
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
|
||||||
|
|
||||||
|
/* Physical Memory Map */
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 1
|
||||||
|
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||||
|
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
|
||||||
|
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
|
||||||
|
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||||
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||||
|
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||||
|
|
||||||
|
/* FLASH and environment organization */
|
||||||
|
#define CONFIG_SYS_NO_FLASH
|
||||||
|
|
||||||
|
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
|
||||||
|
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||||
|
#define CONFIG_ENV_IS_IN_MMC
|
||||||
|
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */
|
||||||
@@ -160,4 +160,9 @@
|
|||||||
/* Reg Power Control 2*/
|
/* Reg Power Control 2*/
|
||||||
#define WDIRESET (1 << 12)
|
#define WDIRESET (1 << 12)
|
||||||
|
|
||||||
|
/* SWx Output Volts */
|
||||||
|
#define SWX_OUT_MASK 0x1F
|
||||||
|
#define SWX_OUT_1_25 0x1A
|
||||||
|
#define SWX_OUT_1_30 0X1C
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
Reference in New Issue
Block a user