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ram: stm32mp1: the property st, phy-cal becomes optional

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This parameter "st,phy-cal" becomes optional and when it is
absent the built-in PHY calibration is done.

It is the case in the helper dtsi file "stm32mp15-ddr.dtsi"
except if DDR_PHY_CAL_SKIP is defined.

This patch also impact the ddr interactive mode
- the registers of the param 'phy.cal' are initialized to 0 when
  "st,phy-cal" is not present in device tree (default behavior when
  DDR_PHY_CAL_SKIP is not activated)
- the info 'cal' field can be use to change the calibration behavior
  - cal=1 => use param phy.cal to initialize the PHY, built-in training
             is skipped
  - cal=0 => param phy.cal is absent, built-in training is used (default)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrick Delaunay
2020-03-06 11:14:11 +01:00
parent d424e6786f
commit 9368bdfebd
6 changed files with 56 additions and 16 deletions
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19
drivers/ram/stm32mp1/stm32mp1_ddr.c
View File

@@ -769,7 +769,8 @@ start:
*/
set_reg(priv, REGPHY_REG, &config->p_reg);
set_reg(priv, REGPHY_TIMING, &config->p_timing);
set_reg(priv, REGPHY_CAL, &config->p_cal);
if (config->p_cal_present)
set_reg(priv, REGPHY_CAL, &config->p_cal);
if (INTERACTIVE(STEP_PHY_INIT))
goto start;
@@ -804,13 +805,16 @@ start:
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
debug("DDR DQS training : ");
if (config->p_cal_present) {
debug("DDR DQS training skipped.\n");
} else {
debug("DDR DQS training : ");
/* 8. Disable Auto refresh and power down by setting
* - RFSHCTL3.dis_au_refresh = 1
* - PWRCTL.powerdown_en = 0
* - DFIMISC.dfiinit_complete_en = 0
*/
stm32mp1_refresh_disable(priv->ctl);
stm32mp1_refresh_disable(priv->ctl);
/* 9. Program PUBL PGCR to enable refresh during training and rank to train
* not done => keep the programed value in PGCR
@@ -818,14 +822,15 @@ start:
/* 10. configure PUBL PIR register to specify which training step to run */
/* warning : RVTRN is not supported by this PUBL */
stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
ddrphy_idone_wait(priv->phy);
ddrphy_idone_wait(priv->phy);
/* 12. set back registers in step 8 to the orginal values if desidered */
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
config->c_reg.pwrctl);
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
config->c_reg.pwrctl);
} /* if (config->p_cal_present) */
/* enable uMCTL2 AXI port 0 and 1 */
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);