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ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.c
Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This commit is contained in:
committed by
Tom Rini
parent
3e01ed00da
commit
909ea9aa26
@@ -5,7 +5,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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# SPDX-License-Identifier: GPL-2.0+
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#
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#
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obj-y += aemif.o
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obj-y += init.o
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obj-y += init.o
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obj-y += psc.o
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obj-y += psc.o
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obj-y += clock.o
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obj-y += clock.o
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@@ -9,13 +9,6 @@
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#ifndef __ASM_ARCH_HARDWARE_K2HK_H
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#ifndef __ASM_ARCH_HARDWARE_K2HK_H
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#define __ASM_ARCH_HARDWARE_K2HK_H
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#define __ASM_ARCH_HARDWARE_K2HK_H
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#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
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#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
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#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
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#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
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#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
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#define K2HK_PLL_CNTRL_BASE 0x02310000
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#define K2HK_PLL_CNTRL_BASE 0x02310000
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#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
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#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
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#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
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#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
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@@ -22,32 +22,6 @@
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typedef volatile unsigned int dv_reg;
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typedef volatile unsigned int dv_reg;
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typedef volatile unsigned int *dv_reg_p;
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typedef volatile unsigned int *dv_reg_p;
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#define ASYNC_EMIF_NUM_CS 4
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#define ASYNC_EMIF_MODE_NOR 0
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#define ASYNC_EMIF_MODE_NAND 1
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#define ASYNC_EMIF_MODE_ONENAND 2
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#define ASYNC_EMIF_PRESERVE -1
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struct async_emif_config {
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unsigned mode;
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unsigned select_strobe;
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unsigned extend_wait;
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unsigned wr_setup;
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unsigned wr_strobe;
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unsigned wr_hold;
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unsigned rd_setup;
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unsigned rd_strobe;
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unsigned rd_hold;
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unsigned turn_around;
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enum {
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ASYNC_EMIF_8 = 0,
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ASYNC_EMIF_16 = 1,
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ASYNC_EMIF_32 = 2,
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} width;
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};
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void init_async_emif(int num_cs, struct async_emif_config *config);
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struct ddr3_phy_config {
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struct ddr3_phy_config {
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unsigned int pllcr;
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unsigned int pllcr;
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unsigned int pgcr1_mask;
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unsigned int pgcr1_mask;
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@@ -145,6 +119,10 @@ struct ddr3_emif_config {
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#define KS2_UART0_BASE 0x02530c00
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#define KS2_UART0_BASE 0x02530c00
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#define KS2_UART1_BASE 0x02531000
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#define KS2_UART1_BASE 0x02531000
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/* AEMIF */
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#define KS2_AEMIF_CNTRL_BASE 0x21000a00
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
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#ifdef CONFIG_SOC_K2HK
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#ifdef CONFIG_SOC_K2HK
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#include <asm/arch/hardware-k2hk.h>
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#include <asm/arch/hardware-k2hk.h>
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#endif
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#endif
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39
arch/arm/include/asm/ti-common/ti-aemif.h
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39
arch/arm/include/asm/ti-common/ti-aemif.h
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@@ -0,0 +1,39 @@
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/*
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* AEMIF definitions
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _AEMIF_H_
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#define _AEMIF_H_
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#define AEMIF_NUM_CS 4
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#define AEMIF_MODE_NOR 0
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#define AEMIF_MODE_NAND 1
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#define AEMIF_MODE_ONENAND 2
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#define AEMIF_PRESERVE -1
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struct aemif_config {
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unsigned mode;
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unsigned select_strobe;
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unsigned extend_wait;
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unsigned wr_setup;
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unsigned wr_strobe;
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unsigned wr_hold;
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unsigned rd_setup;
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unsigned rd_strobe;
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unsigned rd_hold;
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unsigned turn_around;
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enum {
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AEMIF_WIDTH_8 = 0,
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AEMIF_WIDTH_16 = 1,
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AEMIF_WIDTH_32 = 2,
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} width;
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};
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void aemif_init(int num_cs, struct aemif_config *config);
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#endif
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@@ -18,6 +18,7 @@
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#include <asm/mach-types.h>
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#include <asm/mach-types.h>
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#include <asm/arch/emac_defs.h>
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#include <asm/arch/emac_defs.h>
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#include <asm/arch/psc_defs.h>
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#include <asm/arch/psc_defs.h>
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#include <asm/ti-common/ti-aemif.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@@ -39,9 +40,9 @@ unsigned int external_clk[ext_clk_count] = {
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what is that */
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what is that */
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};
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};
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static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
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static struct aemif_config aemif_configs[] = {
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{ /* CS0 */
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{ /* CS0 */
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.mode = ASYNC_EMIF_MODE_NAND,
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.mode = AEMIF_MODE_NAND,
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.wr_setup = 0xf,
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.wr_setup = 0xf,
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.wr_strobe = 0x3f,
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.wr_strobe = 0x3f,
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.wr_hold = 7,
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.wr_hold = 7,
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@@ -49,7 +50,7 @@ static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = {
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.rd_strobe = 0x3f,
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.rd_strobe = 0x3f,
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.rd_hold = 7,
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.rd_hold = 7,
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.turn_around = 3,
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.turn_around = 3,
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.width = ASYNC_EMIF_8,
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.width = AEMIF_WIDTH_8,
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},
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},
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};
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};
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@@ -66,7 +67,7 @@ int dram_init(void)
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gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_RAM_BANK_SIZE);
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CONFIG_MAX_RAM_BANK_SIZE);
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init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config);
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aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
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return 0;
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return 0;
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}
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}
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@@ -14,3 +14,4 @@ obj-y += twserial/
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obj-y += video/
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obj-y += video/
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obj-y += watchdog/
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obj-y += watchdog/
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obj-$(CONFIG_QE) += qe/
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obj-$(CONFIG_QE) += qe/
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obj-y += memory/
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1
drivers/memory/Makefile
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1
drivers/memory/Makefile
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@@ -0,0 +1 @@
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obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
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@@ -8,9 +8,13 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/ti-common/ti-aemif.h>
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#include <asm/arch/clock.h>
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#include <asm/ti-common/davinci_nand.h>
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#define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4)
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#define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60)
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#define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c)
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#define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \
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+ (cs * 4))
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#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
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#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
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#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
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#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
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@@ -31,22 +35,22 @@
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} \
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} \
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} while (0)
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} while (0)
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void configure_async_emif(int cs, struct async_emif_config *cfg)
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static void aemif_configure(int cs, struct aemif_config *cfg)
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{
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{
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unsigned long tmp;
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unsigned long tmp;
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if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
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if (cfg->mode == AEMIF_MODE_NAND) {
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tmp = __raw_readl(&davinci_emif_regs->nandfcr);
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tmp = __raw_readl(AEMIF_NAND_CONTROL);
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tmp |= (1 << cs);
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tmp |= (1 << cs);
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__raw_writel(tmp, &davinci_emif_regs->nandfcr);
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__raw_writel(tmp, AEMIF_NAND_CONTROL);
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} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
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} else if (cfg->mode == AEMIF_MODE_ONENAND) {
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tmp = __raw_readl(&davinci_emif_regs->one_nand_cr);
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tmp = __raw_readl(AEMIF_ONENAND_CONTROL);
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tmp |= (1 << cs);
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tmp |= (1 << cs);
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__raw_writel(tmp, &davinci_emif_regs->one_nand_cr);
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__raw_writel(tmp, AEMIF_ONENAND_CONTROL);
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}
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}
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tmp = __raw_readl(&davinci_emif_regs->abncr[cs]);
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tmp = __raw_readl(AEMIF_CONFIG(cs));
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set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
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set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
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set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
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set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
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@@ -59,13 +63,18 @@ void configure_async_emif(int cs, struct async_emif_config *cfg)
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set_config_field(tmp, TURN_AROUND, cfg->turn_around);
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set_config_field(tmp, TURN_AROUND, cfg->turn_around);
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set_config_field(tmp, WIDTH, cfg->width);
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set_config_field(tmp, WIDTH, cfg->width);
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__raw_writel(tmp, &davinci_emif_regs->abncr[cs]);
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__raw_writel(tmp, AEMIF_CONFIG(cs));
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}
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}
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void init_async_emif(int num_cs, struct async_emif_config *config)
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void aemif_init(int num_cs, struct aemif_config *config)
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{
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{
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int cs;
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int cs;
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if (num_cs > AEMIF_NUM_CS) {
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num_cs = AEMIF_NUM_CS;
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printf("AEMIF: csnum has to be <= 5");
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}
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for (cs = 0; cs < num_cs; cs++)
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for (cs = 0; cs < num_cs; cs++)
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configure_async_emif(cs, config + cs);
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aemif_configure(cs, config + cs);
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}
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}
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@@ -129,6 +129,10 @@
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#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
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#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
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#define CONFIG_SYS_SGMII_RATESCALE 2
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#define CONFIG_SYS_SGMII_RATESCALE 2
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/* AEMIF */
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#define CONFIG_TI_AEMIF
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#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
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/* NAND Configuration */
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/* NAND Configuration */
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_CMD_NAND_ECCLAYOUT
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#define CONFIG_CMD_NAND_ECCLAYOUT
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