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net: mvpp2: adapt the mvpp2_rxq_*_pool_set functions to PPv2.2

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The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Thomas Petazzoni
2017-02-16 06:53:51 +01:00
committed by Stefan Roese
parent c8feeb2b93
commit 8f3e4c3800
1 changed files with 12 additions and 7 deletions
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19
drivers/net/mvpp2.c
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@@ -91,9 +91,11 @@ do { \
#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
#define MVPP2_RXQ_POOL_SHORT_OFFS 20 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
#define MVPP2_RXQ_POOL_SHORT_MASK 0x700000 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
#define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
#define MVPP2_RXQ_POOL_LONG_OFFS 24 #define MVPP2_RXQ_POOL_LONG_OFFS 24
#define MVPP2_RXQ_POOL_LONG_MASK 0x7000000 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
#define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
#define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
#define MVPP2_RXQ_DISABLE_MASK BIT(31) #define MVPP2_RXQ_DISABLE_MASK BIT(31)
@@ -2467,17 +2469,20 @@ static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
int lrxq, int long_pool) int lrxq, int long_pool)
{ {
u32 val; u32 val, mask;
int prxq; int prxq;
/* Get queue physical ID */ /* Get queue physical ID */
prxq = port->rxqs[lrxq]->id; prxq = port->rxqs[lrxq]->id;
val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); if (port->priv->hw_version == MVPP21)
val &= ~MVPP2_RXQ_POOL_LONG_MASK; mask = MVPP21_RXQ_POOL_LONG_MASK;
val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & else
MVPP2_RXQ_POOL_LONG_MASK); mask = MVPP22_RXQ_POOL_LONG_MASK;
val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
val &= ~mask;
val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
} }