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mmc: tmio: Switch to clock framework

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Switch the driver to using clk_get_rate()/clk_set_rate() instead of
caching the mclk frequency in it's private data. This is required on
the SDHI variant of the controller, where the upstream mclk need to
be adjusted when using UHS modes.

Platforms which do not support clock framework or do not support it
in eg. SPL default to 100 MHz clock.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
---
V2: - Fix build on certain platforms using SPL without clock framework
V3: - Turn clk_get_rate into a callback and fill it as needed on both
      renesas and socionext platforms
This commit is contained in:
Marek Vasut
2018-06-13 08:02:55 +02:00
committed by Marek Vasut
parent eb2acbafff
commit 8ec6a04b6b
4 changed files with 51 additions and 22 deletions
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17
drivers/mmc/tmio-common.c
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@@ -555,16 +555,24 @@ static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
}
static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
{
return priv->clk_get_rate(priv);
}
static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
struct mmc *mmc)
{
unsigned int divisor;
u32 val, tmp;
ulong mclk;
if (!mmc->clock)
return;
divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
mclk = tmio_sd_clk_get_rate(priv);
divisor = DIV_ROUND_UP(mclk, mmc->clock);
if (divisor <= 1)
val = (priv->caps & TMIO_SD_CAP_RCAR) ?
@@ -708,6 +716,7 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
fdt_addr_t base;
ulong mclk;
int ret;
base = devfdt_get_addr(dev);
@@ -750,10 +759,12 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
tmio_sd_host_init(priv);
mclk = tmio_sd_clk_get_rate(priv);
plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
plat->cfg.f_min = priv->mclk /
plat->cfg.f_min = mclk /
(priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
plat->cfg.f_max = priv->mclk;
plat->cfg.f_max = mclk;
plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
upriv->mmc = &plat->mmc;