Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
  cleanups
- fsl-crypto: RNG support and bug fixes

doc/README.fsl-esdhc

@@ -1,19 +1,5 @@
 Freescale esdhc-specific options
 
-	- CONFIG_FSL_ESDHC_ADAPTER_IDENT
-		Support Freescale adapter card type identification. This is implemented by
-		operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC
-		Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot.
-
-		SDHC Card ID[0:2]	Adapter Card Type
-		0b000			reserved
-		0b001			eMMC Card Rev4.5
-		0b010			SD/MMC Legacy Card
-		0b011			eMMC Card Rev4.4
-		0b100			reserved
-		0b101			MMC Card
-		0b110			SD Card Rev2.0/3.0
-		0b111			No card is present
 	- CONFIG_SYS_FSL_ESDHC_LE
 		ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
 		determined by ESDHC IP's endian mode or processor's endian mode.

doc/device-tree-bindings/spi/spi-mcf-dspi.txt

@@ -13,6 +13,10 @@ Optional properties:
 - ctar-params: CTAR0 to 7 register configuration, as an array
   of 8 integer fields for each register, where each register
   is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>.
+- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
+  select and the start of clock signal, at the start of a transfer.
+- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
+  signal and deactivating chip select, at the end of a transfer.
 
 Example: