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ddr: imx8m: Return error values from LPDDR4 training

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In cases when the same SPL should run on boards with i.MX8MM, that
differ in DDR configuration, it is necessary to try different
parameters and check if the training done by the firmware suceeds or
not.

Therefore we return the DDR training/initialization success to the
upper layer in order to be able to retry with different settings if
necessary.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
This commit is contained in:
Frieder Schrempf
2019-12-11 10:01:19 +00:00
committed by Stefano Babic
parent 162c72c804
commit 83083febf5
4 changed files with 23 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/ddr/imx/imx8m/ddr_init.c
View File

@@ -20,9 +20,10 @@ void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
}
}
void ddr_init(struct dram_timing_info *dram_timing)
int ddr_init(struct dram_timing_info *dram_timing)
{
unsigned int tmp, initial_drate, target_freq;
int ret;
debug("DDRINFO: start DRAM init\n");
@@ -98,7 +99,11 @@ void ddr_init(struct dram_timing_info *dram_timing)
* accessing relevant PUB registers
*/
debug("DDRINFO:ddrphy config start\n");
ddr_cfg_phy(dram_timing);
ret = ddr_cfg_phy(dram_timing);
if (ret)
return ret;
debug("DDRINFO: ddrphy config done\n");
/*
@@ -165,4 +170,6 @@ void ddr_init(struct dram_timing_info *dram_timing)
/* save the dram timing config into memory */
dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
return 0;
}

9
drivers/ddr/imx/imx8m/ddrphy_train.c
View File

@@ -8,13 +8,14 @@
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
void ddr_cfg_phy(struct dram_timing_info *dram_timing)
int ddr_cfg_phy(struct dram_timing_info *dram_timing)
{
struct dram_cfg_param *dram_cfg;
struct dram_fsp_msg *fsp_msg;
unsigned int num;
int i = 0;
int j = 0;
int ret;
/* initialize PHY configuration */
dram_cfg = dram_timing->ddrphy_cfg;
@@ -60,7 +61,9 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing)
dwc_ddrphy_apb_wr(0xd0099, 0x0);
/* Wait for the training firmware to complete */
wait_ddrphy_training_complete();
ret = wait_ddrphy_training_complete();
if (ret)
return ret;
/* Halt the microcontroller. */
dwc_ddrphy_apb_wr(0xd0099, 0x1);
@@ -83,4 +86,6 @@ void ddr_cfg_phy(struct dram_timing_info *dram_timing)
/* save the ddr PHY trained CSR in memory for low power use */
ddrphy_trained_csr_save(ddrphy_trained_csr, ddrphy_trained_csr_num);
return 0;
}

8
drivers/ddr/imx/imx8m/ddrphy_utils.c
View File

@@ -84,7 +84,7 @@ static inline void decode_streaming_message(void)
debug("\n");
}
void wait_ddrphy_training_complete(void)
int wait_ddrphy_training_complete(void)
{
unsigned int mail;
@@ -95,10 +95,10 @@ void wait_ddrphy_training_complete(void)
decode_streaming_message();
} else if (mail == 0x07) {
debug("Training PASS\n");
break;
return 0;
} else if (mail == 0xff) {
printf("Training FAILED\n");
break;
debug("Training FAILED\n");
return -1;
}
}
}