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ppc4xx: Consolidate PPC4xx EBC defines

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This patch removes all EBC related defines from the PPC4xx headers
ppc405.h and ppc440.h and introduces a new header

include/asm-ppc/ppc4xx-ebc.h

with all those defines.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2008-06-24 17:18:50 +02:00
parent e321801bed
commit 7ee2619c20
4 changed files with 157 additions and 201 deletions
Download Patch File Download Diff File Expand all files Collapse all files

114
include/ppc405.h
View File

@@ -366,120 +366,6 @@
#define UIC_EXT6 0x00000001 /* External interrupt 6 */
#endif /* defined(CONFIG_405EZ) */
/******************************************************************************
* External Bus Controller (EBC)
*****************************************************************************/
/* Bank Configuration Register */
#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \
EBC_BXCR_BAS_MASK) << 0)
#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)
#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0)
#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1)
#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2)
#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3)
#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4)
#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5)
#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6)
#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7)
#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3)
#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0)
#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1)
#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2)
#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3)
#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3)
#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0)
#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1)
#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3)
/* Bank Access Parameter Register */
#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1)
#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0)
#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \
(static_cast(unsigned long, n)) \
& 0xFF)
#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \
(static_cast(unsigned long, n)) \
& 0x1F)
#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \
(static_cast(unsigned long, n)) \
& 0x7)
#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0)
#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1)
#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3)
#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0)
#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1)
#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2)
#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3)
#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \
(static_cast(unsigned long, n)) \
& 0x3)
#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \
(static_cast(unsigned long, n)) \
& 0x3)
#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \
(static_cast(unsigned long, n)) \
& 0x3)
#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \
(static_cast(unsigned long, n)) \
& 0x3)
#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \
(static_cast(unsigned long, n)) \
& 0x7)
#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1)
#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0)
#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0)
#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1)
#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0)
#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1)
#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0)
#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1)
/* Configuration Register */
#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1)
#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0)
#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1)
#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1)
#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0)
#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1)
#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7)
#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0)
#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1)
#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2)
#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3)
#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4)
#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5)
#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6)
#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7)
#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1)
#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0)
#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1)
#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1)
#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0)
#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1)
#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1)
#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0)
#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1)
#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1)
#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0)
#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1)
#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1)
#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0)
#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1)
#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1)
#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0)
#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1)
#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F)
#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \
(static_cast(unsigned long, n)) \
& 0x1F)
#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3)
#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0)
#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1)
#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2)
#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3)
#ifndef CONFIG_405EP
/******************************************************************************
* Decompression Controller