mirror of
https://xff.cz/git/u-boot/
synced 2025-09-04 10:12:14 +02:00
Convert CONFIG_ESDHC_DETECT_QUIRK to Kconfig
This converts the following to Kconfig: CONFIG_ESDHC_DETECT_QUIRK Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
@@ -166,4 +166,25 @@ defined(CONFIG_TARGET_LX2160ARDB)
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#define QIXIS_ESDHC_NO_ADAPTER 0x7
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#define QIXIS_ESDHC_NO_ADAPTER 0x7
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#endif
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#endif
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/*
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* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
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*/
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static inline u8 qixis_esdhc_detect_quirk(void)
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{
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/*
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* SDHC1 Card ID:
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* Specifies the type of card installed in the SDHC1 adapter slot.
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* 000= (reserved)
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* 001= eMMC V4.5 adapter is installed.
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* 010= SD/MMC 3.3V adapter is installed.
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* 011= eMMC V4.4 adapter is installed.
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* 100= eMMC V5.0 adapter is installed.
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* 101= MMC card/Legacy (3.3V) adapter is installed.
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* 110= SDCard V2/V3 adapter installed.
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* 111= no adapter is installed.
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*/
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return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
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QIXIS_ESDHC_NO_ADAPTER);
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}
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#endif
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#endif
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@@ -356,27 +356,6 @@ int checkboard(void)
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}
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}
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#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
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#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
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/*
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* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
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*/
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u8 qixis_esdhc_detect_quirk(void)
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{
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/*
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* SDHC1 Card ID:
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* Specifies the type of card installed in the SDHC1 adapter slot.
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* 000= (reserved)
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* 001= eMMC V4.5 adapter is installed.
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* 010= SD/MMC 3.3V adapter is installed.
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* 011= eMMC V4.4 adapter is installed.
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* 100= eMMC V5.0 adapter is installed.
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* 101= MMC card/Legacy (3.3V) adapter is installed.
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* 110= SDCard V2/V3 adapter installed.
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* 111= no adapter is installed.
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*/
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return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
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QIXIS_ESDHC_NO_ADAPTER);
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}
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static void esdhc_adapter_card_ident(void)
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static void esdhc_adapter_card_ident(void)
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{
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{
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u8 card_id, val;
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u8 card_id, val;
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@@ -71,6 +71,7 @@ CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_FLASH_CFI_DRIVER=y
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@@ -65,6 +65,7 @@ CONFIG_MPC8XXX_GPIO=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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@@ -68,6 +68,7 @@ CONFIG_MPC8XXX_GPIO=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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@@ -90,6 +90,7 @@ CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_FLASH_CFI_DRIVER=y
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@@ -86,6 +86,7 @@ CONFIG_MPC8XXX_GPIO=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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@@ -79,6 +79,7 @@ CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_FLASH_CFI_DRIVER=y
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@@ -59,6 +59,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_FLASH_CFI_DRIVER=y
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@@ -62,6 +62,7 @@ CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_FLASH_CFI_DRIVER=y
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@@ -83,6 +83,7 @@ CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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@@ -64,6 +64,7 @@ CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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@@ -78,6 +78,7 @@ CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EARLY_INIT=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_NAND_FSL_IFC=y
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@@ -73,6 +73,7 @@ CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_FLASH_CFI_DRIVER=y
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@@ -69,6 +69,7 @@ CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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@@ -76,6 +76,7 @@ CONFIG_I2C_MUX=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_I2C_MUX_PCA954x=y
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_SYS_I2C_EEPROM_ADDR=0x57
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CONFIG_FSL_ESDHC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_ESDHC_DETECT_QUIRK=y
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CONFIG_MTD=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_EON=y
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@@ -844,6 +844,10 @@ config SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH
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depends on FSL_ESDHC
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depends on FSL_ESDHC
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default 1
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default 1
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config ESDHC_DETECT_QUIRK
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bool "QIXIS-based eSDHC quirk detection"
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depends on FSL_ESDHC && FSL_QIXIS
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config FSL_ESDHC_IMX
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config FSL_ESDHC_IMX
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bool "Freescale/NXP i.MX eSDHC controller support"
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bool "Freescale/NXP i.MX eSDHC controller support"
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help
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help
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@@ -30,6 +30,7 @@
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#include <linux/iopoll.h>
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#include <linux/iopoll.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma-mapping.h>
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#include <sdhci.h>
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#include <sdhci.h>
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#include "../../board/freescale/common/qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@@ -773,7 +774,7 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
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struct fsl_esdhc *regs = priv->esdhc_regs;
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struct fsl_esdhc *regs = priv->esdhc_regs;
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#ifdef CONFIG_ESDHC_DETECT_QUIRK
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#ifdef CONFIG_ESDHC_DETECT_QUIRK
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if (CONFIG_ESDHC_DETECT_QUIRK)
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if (qixis_esdhc_detect_quirk())
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return 1;
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return 1;
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#endif
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#endif
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if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS)
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if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS)
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@@ -305,10 +305,6 @@
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#define CONFIG_FSL_MEMAC
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#define CONFIG_FSL_MEMAC
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/* MMC */
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#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
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QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
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#define COMMON_ENV \
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#define COMMON_ENV \
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"kernelheader_addr_r=0x80200000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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@@ -238,14 +238,6 @@
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*/
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*/
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#define FSL_QIXIS_BRDCFG9_QSPI 0x1
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#define FSL_QIXIS_BRDCFG9_QSPI 0x1
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/*
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* MMC
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*/
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#ifdef CONFIG_MMC
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#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
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QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
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#endif
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/*
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/*
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* RTC configuration
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* RTC configuration
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*/
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*/
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@@ -11,16 +11,6 @@
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/* RTC */
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/* RTC */
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#define CONFIG_SYS_RTC_BUS_NUM 0
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#define CONFIG_SYS_RTC_BUS_NUM 0
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/*
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* MMC
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*/
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#ifdef CONFIG_MMC
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#ifndef __ASSEMBLY__
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u8 qixis_esdhc_detect_quirk(void);
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#endif
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#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
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#endif
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/* MAC/PHY configuration */
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/* MAC/PHY configuration */
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/* EEPROM */
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/* EEPROM */
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@@ -13,16 +13,6 @@
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/* RTC */
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/* RTC */
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#define CONFIG_SYS_RTC_BUS_NUM 0
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#define CONFIG_SYS_RTC_BUS_NUM 0
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/*
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* MMC
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*/
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#ifdef CONFIG_MMC
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#ifndef __ASSEMBLY__
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u8 qixis_esdhc_detect_quirk(void);
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#endif
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#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
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#endif
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/* EEPROM */
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/* EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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