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	SPEAr: explicitly select clk src for UART
UART in u-boot intends to run on 48MHz clock supplied by USB PLL. Explicitly select the intended clock source. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
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					committed by
					
						 Albert ARIBAUD
						Albert ARIBAUD
					
				
			
			
				
	
			
			
			
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					7c885a0e55
				
			| @@ -30,7 +30,7 @@ int arch_cpu_init(void) | |||||||
| { | { | ||||||
| 	struct misc_regs *const misc_p = | 	struct misc_regs *const misc_p = | ||||||
| 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE; | 	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE; | ||||||
| 	u32 periph1_clken; | 	u32 periph1_clken, periph_clk_cfg; | ||||||
|  |  | ||||||
| 	periph1_clken = readl(&misc_p->periph1_clken); | 	periph1_clken = readl(&misc_p->periph1_clken); | ||||||
|  |  | ||||||
| @@ -42,6 +42,11 @@ int arch_cpu_init(void) | |||||||
|  |  | ||||||
| #if defined(CONFIG_PL011_SERIAL) | #if defined(CONFIG_PL011_SERIAL) | ||||||
| 	periph1_clken |= MISC_UART0ENB; | 	periph1_clken |= MISC_UART0ENB; | ||||||
|  |  | ||||||
|  | 	periph_clk_cfg = readl(&misc_p->periph_clk_cfg); | ||||||
|  | 	periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK; | ||||||
|  | 	periph_clk_cfg |= CONFIG_SPEAR_UART48M; | ||||||
|  | 	writel(periph_clk_cfg, &misc_p->periph_clk_cfg); | ||||||
| #endif | #endif | ||||||
| #if defined(CONFIG_DESIGNWARE_ETH) | #if defined(CONFIG_DESIGNWARE_ETH) | ||||||
| 	periph1_clken |= MISC_ETHENB; | 	periph1_clken |= MISC_ETHENB; | ||||||
|   | |||||||
| @@ -110,6 +110,8 @@ struct misc_regs { | |||||||
| /* PERIPH_CLK_CFG value */ | /* PERIPH_CLK_CFG value */ | ||||||
| #define MISC_GPT3SYNTH			0x00000400 | #define MISC_GPT3SYNTH			0x00000400 | ||||||
| #define MISC_GPT4SYNTH			0x00000800 | #define MISC_GPT4SYNTH			0x00000800 | ||||||
|  | #define CONFIG_SPEAR_UART48M		0 | ||||||
|  | #define CONFIG_SPEAR_UARTCLKMSK		(0x1 << 4) | ||||||
|  |  | ||||||
| /* PRSC_CLK_CFG value */ | /* PRSC_CLK_CFG value */ | ||||||
| /* | /* | ||||||
|   | |||||||
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