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imx8mq: Update the ddrc QoS setting for B1 chip

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Update the ddrc Qos setting for B1 to align with B0's setting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Tested-by: Robby Cai <robby.cai@nxp.com>
This commit is contained in:
Bai Ping
2019-08-08 09:59:05 +00:00
committed by Stefano Babic
parent ca729cd16c
commit 7b14cc991b
2 changed files with 14 additions and 7 deletions
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5
drivers/ddr/imx/imx8m/lpddr4_init.c
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@@ -54,7 +54,10 @@ void ddr_init(struct dram_timing_info *dram_timing)
reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
debug("DDRINFO: cfg clk\n");
dram_pll_init(MHZ(750));
if (is_imx8mq())
dram_pll_init(MHZ(800));
else
dram_pll_init(MHZ(750));
/*
* release [0]ddr1_preset_n, [1]ddr1_core_reset_n,