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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Browse Source
This commit is contained in:
Tom Rini
2015-08-02 07:40:37 -04:00
parent 8968b914be f85764cc1f
commit 7a1af7a79b
81 changed files with 4303 additions and 552 deletions
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16
arch/arm/Kconfig
View File

@@ -578,6 +578,13 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
config TARGET_MX6UL_14X14_EVK
bool "Support mx6ul_14x14_evk"
select CPU_V7
select DM
select DM_THERMAL
select SUPPORT_SPL
config TARGET_GW_VENTANA
bool "Support gw_ventana"
select CPU_V7
@@ -625,14 +632,6 @@ config RMOBILE
bool "Renesas ARM SoCs"
select CPU_V7
config TARGET_CM_FX6
bool "Support cm_fx6"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_GPIO
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
@@ -920,6 +919,7 @@ source "board/freescale/mx6qsabreauto/Kconfig"
source "board/freescale/mx6sabresd/Kconfig"
source "board/freescale/mx6slevk/Kconfig"
source "board/freescale/mx6sxsabresd/Kconfig"
source "board/freescale/mx6ul_14x14_evk/Kconfig"
source "board/freescale/vf610twr/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/genesi/mx51_efikamx/Kconfig"

13
arch/arm/cpu/armv7/mx6/Kconfig
View File

@@ -25,17 +25,26 @@ config MX6SL
config MX6SX
bool
config MX6UL
select SYS_L2CACHE_OFF
bool
choice
prompt "MX6 board select"
optional
config TARGET_CM_FX6
bool "Support CM-FX6"
select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_SECOMX6
bool "Support secomx6 boards"
select CPU_V7
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
select CPU_V7
endchoice

209
arch/arm/cpu/armv7/mx6/clock.c
View File

@@ -81,19 +81,32 @@ void enable_usboh3_clk(unsigned char enable)
#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
void enable_enet_clk(unsigned char enable)
{
u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
u32 mask, *addr;
if (is_cpu_type(MXC_CPU_MX6UL)) {
mask = MXC_CCM_CCGR3_ENET_MASK;
addr = &imx_ccm->CCGR3;
} else {
mask = MXC_CCM_CCGR1_ENET_MASK;
addr = &imx_ccm->CCGR1;
}
if (enable)
setbits_le32(&imx_ccm->CCGR1, mask);
setbits_le32(addr, mask);
else
clrbits_le32(&imx_ccm->CCGR1, mask);
clrbits_le32(addr, mask);
}
#endif
#ifdef CONFIG_MXC_UART
void enable_uart_clk(unsigned char enable)
{
u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
u32 mask;
if (is_cpu_type(MXC_CPU_MX6UL))
mask = MXC_CCM_CCGR5_UART_MASK;
else
mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
if (enable)
setbits_le32(&imx_ccm->CCGR5, mask);
@@ -102,25 +115,6 @@ void enable_uart_clk(unsigned char enable)
}
#endif
#ifdef CONFIG_SPI
/* spi_num can be from 0 - 4 */
int enable_cspi_clock(unsigned char enable, unsigned spi_num)
{
u32 mask;
if (spi_num > 4)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
if (enable)
setbits_le32(&imx_ccm->CCGR1, mask);
else
clrbits_le32(&imx_ccm->CCGR1, mask);
return 0;
}
#endif
#ifdef CONFIG_MMC
int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
{
@@ -145,6 +139,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
u32 reg;
u32 mask;
u32 *addr;
if (i2c_num > 3)
return -EINVAL;
@@ -159,14 +154,19 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR2);
} else {
mask = MXC_CCM_CCGR_CG_MASK
<< (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
reg = __raw_readl(&imx_ccm->CCGR1);
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
mask = MXC_CCM_CCGR6_I2C4_MASK;
addr = &imx_ccm->CCGR6;
} else {
mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
addr = &imx_ccm->CCGR1;
}
reg = __raw_readl(addr);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR1);
__raw_writel(reg, addr);
}
return 0;
}
@@ -227,9 +227,11 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
switch (pll) {
case PLL_BUS:
if (pfd_num == 3) {
/* No PFD3 on PPL2 */
return 0;
if (!is_cpu_type(MXC_CPU_MX6UL)) {
if (pfd_num == 3) {
/* No PFD3 on PPL2 */
return 0;
}
}
div = __raw_readl(&imx_ccm->analog_pfd_528);
freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
@@ -261,10 +263,12 @@ static u32 get_mcu_main_clk(void)
u32 get_periph_clk(void)
{
u32 reg, freq = 0;
u32 reg, div = 0, freq = 0;
reg = __raw_readl(&imx_ccm->cbcdr);
if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
reg = __raw_readl(&imx_ccm->cbcmr);
reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
@@ -304,7 +308,7 @@ u32 get_periph_clk(void)
}
}
return freq;
return freq / (div + 1);
}
static u32 get_ipg_clk(void)
@@ -323,10 +327,12 @@ static u32 get_ipg_per_clk(void)
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
#endif
if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
return MXC_HCLK; /* OSC 24Mhz */
}
perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1);
@@ -337,10 +343,13 @@ static u32 get_uart_clk(void)
u32 reg, uart_podf;
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
#endif
if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
}
reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
@@ -352,8 +361,14 @@ static u32 get_cspi_clk(void)
u32 reg, cspi_podf;
reg = __raw_readl(&imx_ccm->cscdr2);
reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
return MXC_HCLK / (cspi_podf + 1);
}
return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
}
@@ -405,47 +420,60 @@ static u32 get_emi_slow_clk(void)
return root_freq / (emi_slow_podf + 1);
}
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
u32 freq, podf;
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
u32 freq, podf, per2_clk2_podf;
switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
case 0:
freq = decode_pll(PLL_BUS, MXC_HCLK);
break;
case 1:
freq = mxc_get_pll_pfd(PLL_BUS, 2);
break;
case 2:
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
/* static / 2 divider */
freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
is_cpu_type(MXC_CPU_MX6SL)) {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
if (is_cpu_type(MXC_CPU_MX6SL)) {
if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
freq = MXC_HCLK;
else
freq = decode_pll(PLL_USBOTG, MXC_HCLK);
} else {
if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
freq = decode_pll(PLL_BUS, MXC_HCLK);
else
freq = decode_pll(PLL_USBOTG, MXC_HCLK);
}
} else {
per2_clk2_podf = 0;
switch ((cbcmr &
MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
case 0:
freq = decode_pll(PLL_BUS, MXC_HCLK);
break;
case 1:
freq = mxc_get_pll_pfd(PLL_BUS, 2);
break;
case 2:
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
/* static / 2 divider */
freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
break;
}
}
return freq / (podf + 1) / (per2_clk2_podf + 1);
} else {
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
return get_periph_clk() / (podf + 1);
}
return freq / (podf + 1);
}
#else
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
return get_periph_clk() / (mmdc_ch0_podf + 1);
}
#endif
#ifdef CONFIG_MX6SX
#ifdef CONFIG_FSL_QSPI
/* qspi_num can be from 0 - 1 */
void enable_qspi_clk(int qspi_num)
{
@@ -606,6 +634,7 @@ u32 imx_get_fecclk(void)
return mxc_get_clock(MXC_IPG_CLK);
}
#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
static int enable_enet_pll(uint32_t en)
{
struct mxc_ccm_reg *const imx_ccm
@@ -630,8 +659,9 @@ static int enable_enet_pll(uint32_t en)
writel(reg, &imx_ccm->analog_pll_enet);
return 0;
}
#endif
#ifndef CONFIG_MX6SX
#ifdef CONFIG_CMD_SATA
static void ungate_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
@@ -640,18 +670,7 @@ static void ungate_sata_clock(void)
/* Enable SATA clock. */
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
#endif
static void ungate_pcie_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
(struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* Enable PCIe clock. */
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
}
#ifndef CONFIG_MX6SX
int enable_sata_clock(void)
{
ungate_sata_clock();
@@ -667,6 +686,16 @@ void disable_sata_clock(void)
}
#endif
#ifdef CONFIG_PCIE_IMX
static void ungate_pcie_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
(struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* Enable PCIe clock. */
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
}
int enable_pcie_clock(void)
{
struct anatop_regs *anatop_regs =
@@ -706,7 +735,7 @@ int enable_pcie_clock(void)
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
/* Party time! Ungate the clock to the PCIe. */
#ifndef CONFIG_MX6SX
#ifdef CONFIG_CMD_SATA
ungate_sata_clock();
#endif
ungate_pcie_clock();
@@ -714,6 +743,7 @@ int enable_pcie_clock(void)
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
BM_ANADIG_PLL_ENET_ENABLE_PCIE);
}
#endif
#ifdef CONFIG_SECURE_BOOT
void hab_caam_clock_enable(unsigned char enable)
@@ -856,6 +886,11 @@ void enable_ipu_clock(void)
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
if (is_mx6dqp()) {
setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
}
}
#endif
/***************************************************/

61
arch/arm/cpu/armv7/mx6/ddr.c
View File

@@ -71,6 +71,50 @@ void mx6sx_dram_iocfg(unsigned width,
}
#endif
#ifdef CONFIG_MX6UL
void mx6ul_dram_iocfg(unsigned width,
const struct mx6ul_iomux_ddr_regs *ddr,
const struct mx6ul_iomux_grp_regs *grp)
{
struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
/* DDR IO TYPE */
writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
/* CLOCK */
writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
/* ADDRESS */
writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
/* Control */
writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
/* Data Strobes */
writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
/* Data */
writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
}
#endif
#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
/* Configure MX6DQ mmdc iomux */
void mx6dq_dram_iocfg(unsigned width,
@@ -243,19 +287,17 @@ void mx6sdl_dram_iocfg(unsigned width,
*/
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#ifdef CONFIG_MX6SX
#define MMDC1(entry, value) do {} while (0)
#else
#define MMDC1(entry, value) do { mmdc1->entry = value; } while (0)
#endif
#define MMDC1(entry, value) do { \
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
mmdc1->entry = value; \
} while (0)
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
const struct mx6_mmdc_calibration *calib,
const struct mx6_ddr3_cfg *ddr3_cfg)
{
volatile struct mmdc_p_regs *mmdc0;
#ifndef CONFIG_MX6SX
volatile struct mmdc_p_regs *mmdc1;
#endif
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -270,9 +312,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
#ifndef CONFIG_MX6SX
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
#endif
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {

176
arch/arm/cpu/armv7/mx6/hab.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
* Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -111,6 +111,153 @@
* +------------+ + CSF_PAD_SIZE
*/
#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
struct record {
uint8_t tag; /* Tag */
uint8_t len[2]; /* Length */
uint8_t par; /* Version */
uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
bool any_rec_flag;
};
char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
"RSN = HAB_ENG_FAIL (0x30)\n",
"RSN = HAB_INV_ADDRESS (0x22)\n",
"RSN = HAB_INV_ASSERTION (0x0C)\n",
"RSN = HAB_INV_CALL (0x28)\n",
"RSN = HAB_INV_CERTIFICATE (0x21)\n",
"RSN = HAB_INV_COMMAND (0x06)\n",
"RSN = HAB_INV_CSF (0x11)\n",
"RSN = HAB_INV_DCD (0x27)\n",
"RSN = HAB_INV_INDEX (0x0F)\n",
"RSN = HAB_INV_IVT (0x05)\n",
"RSN = HAB_INV_KEY (0x1D)\n",
"RSN = HAB_INV_RETURN (0x1E)\n",
"RSN = HAB_INV_SIGNATURE (0x18)\n",
"RSN = HAB_INV_SIZE (0x17)\n",
"RSN = HAB_MEM_FAIL (0x2E)\n",
"RSN = HAB_OVR_COUNT (0x2B)\n",
"RSN = HAB_OVR_STORAGE (0x2D)\n",
"RSN = HAB_UNS_ALGORITHM (0x12)\n",
"RSN = HAB_UNS_COMMAND (0x03)\n",
"RSN = HAB_UNS_ENGINE (0x0A)\n",
"RSN = HAB_UNS_ITEM (0x24)\n",
"RSN = HAB_UNS_KEY (0x1B)\n",
"RSN = HAB_UNS_PROTOCOL (0x14)\n",
"RSN = HAB_UNS_STATE (0x09)\n",
"RSN = INVALID\n",
NULL};
char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
"STS = HAB_FAILURE (0x33)\n",
"STS = HAB_WARNING (0x69)\n",
"STS = INVALID\n",
NULL};
char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
"ENG = HAB_ENG_SCC (0x03)\n",
"ENG = HAB_ENG_RTIC (0x05)\n",
"ENG = HAB_ENG_SAHARA (0x06)\n",
"ENG = HAB_ENG_CSU (0x0A)\n",
"ENG = HAB_ENG_SRTC (0x0C)\n",
"ENG = HAB_ENG_DCP (0x1B)\n",
"ENG = HAB_ENG_CAAM (0x1D)\n",
"ENG = HAB_ENG_SNVS (0x1E)\n",
"ENG = HAB_ENG_OCOTP (0x21)\n",
"ENG = HAB_ENG_DTCP (0x22)\n",
"ENG = HAB_ENG_ROM (0x36)\n",
"ENG = HAB_ENG_HDCP (0x24)\n",
"ENG = HAB_ENG_RTL (0x77)\n",
"ENG = HAB_ENG_SW (0xFF)\n",
"ENG = INVALID\n",
NULL};
char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
"CTX = HAB_CTX_FAB (0xFF)\n",
"CTX = HAB_CTX_ENTRY (0xE1)\n",
"CTX = HAB_CTX_TARGET (0x33)\n",
"CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
"CTX = HAB_CTX_DCD (0xDD)\n",
"CTX = HAB_CTX_CSF (0xCF)\n",
"CTX = HAB_CTX_COMMAND (0xC0)\n",
"CTX = HAB_CTX_AUT_DAT (0xDB)\n",
"CTX = HAB_CTX_ASSERT (0xA0)\n",
"CTX = HAB_CTX_EXIT (0xEE)\n",
"CTX = INVALID\n",
NULL};
uint8_t hab_statuses[5] = {
HAB_STS_ANY,
HAB_FAILURE,
HAB_WARNING,
HAB_SUCCESS,
-1
};
uint8_t hab_reasons[26] = {
HAB_RSN_ANY,
HAB_ENG_FAIL,
HAB_INV_ADDRESS,
HAB_INV_ASSERTION,
HAB_INV_CALL,
HAB_INV_CERTIFICATE,
HAB_INV_COMMAND,
HAB_INV_CSF,
HAB_INV_DCD,
HAB_INV_INDEX,
HAB_INV_IVT,
HAB_INV_KEY,
HAB_INV_RETURN,
HAB_INV_SIGNATURE,
HAB_INV_SIZE,
HAB_MEM_FAIL,
HAB_OVR_COUNT,
HAB_OVR_STORAGE,
HAB_UNS_ALGORITHM,
HAB_UNS_COMMAND,
HAB_UNS_ENGINE,
HAB_UNS_ITEM,
HAB_UNS_KEY,
HAB_UNS_PROTOCOL,
HAB_UNS_STATE,
-1
};
uint8_t hab_contexts[12] = {
HAB_CTX_ANY,
HAB_CTX_FAB,
HAB_CTX_ENTRY,
HAB_CTX_TARGET,
HAB_CTX_AUTHENTICATE,
HAB_CTX_DCD,
HAB_CTX_CSF,
HAB_CTX_COMMAND,
HAB_CTX_AUT_DAT,
HAB_CTX_ASSERT,
HAB_CTX_EXIT,
-1
};
uint8_t hab_engines[16] = {
HAB_ENG_ANY,
HAB_ENG_SCC,
HAB_ENG_RTIC,
HAB_ENG_SAHARA,
HAB_ENG_CSU,
HAB_ENG_SRTC,
HAB_ENG_DCP,
HAB_ENG_CAAM,
HAB_ENG_SNVS,
HAB_ENG_OCOTP,
HAB_ENG_DTCP,
HAB_ENG_ROM,
HAB_ENG_HDCP,
HAB_ENG_RTL,
HAB_ENG_SW,
-1
};
bool is_hab_enabled(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -122,6 +269,28 @@ bool is_hab_enabled(void)
return (reg & 0x2) == 0x2;
}
static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
{
uint8_t idx = 0;
uint8_t element = list[idx];
while (element != -1) {
if (element == tgt)
return idx;
element = list[++idx];
}
return -1;
}
void process_event_record(uint8_t *event_data, size_t bytes)
{
struct record *rec = (struct record *)event_data;
printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
}
void display_event(uint8_t *event_data, size_t bytes)
{
uint32_t i;
@@ -137,6 +306,8 @@ void display_event(uint8_t *event_data, size_t bytes)
else
printf(" 0x%02x", event_data[i]);
}
process_event_record(event_data, bytes);
}
int get_hab_status(void)
@@ -252,7 +423,8 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
* do cache flushes. don't think any
* exist, so we ignore them.
*/
writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
if (!is_mx6dqp())
writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
} else if (is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO)) {
writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);

25
arch/arm/cpu/armv7/mx6/soc.c
View File

@@ -62,12 +62,12 @@ u32 get_cpu_rev(void)
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 reg = readl(&anatop->digprog_sololite);
u32 type = ((reg >> 16) & 0xff);
u32 major;
u32 major, cfg = 0;
if (type != MXC_CPU_MX6SL) {
reg = readl(&anatop->digprog);
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
u32 cfg = readl(&scu->config) & 3;
cfg = readl(&scu->config) & 3;
type = ((reg >> 16) & 0xff);
if (type == MXC_CPU_MX6DL) {
if (!cfg)
@@ -81,6 +81,13 @@ u32 get_cpu_rev(void)
}
major = ((reg >> 8) & 0xff);
if ((major >= 1) &&
((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
major--;
type = MXC_CPU_MX6QP;
if (cfg == 1)
type = MXC_CPU_MX6DP;
}
reg &= 0xff; /* mx6 silicon revision */
return (type << 12) | (reg + (0x10 * (major + 1)));
}
@@ -309,11 +316,10 @@ static void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
#ifdef CONFIG_MX6SX
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
writew(enable, &wdog3->wmcr);
#endif
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
writew(enable, &wdog3->wmcr);
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
@@ -335,9 +341,12 @@ static void set_ahb_rate(u32 val)
static void clear_mmdc_ch_mask(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 reg;
reg = readl(&mxc_ccm->ccdr);
/* Clear MMDC channel mask */
writel(0, &mxc_ccm->ccdr);
reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
writel(reg, &mxc_ccm->ccdr);
}
static void init_bandgap(void)
@@ -520,7 +529,7 @@ void s_init(void)
u32 mask528;
u32 reg, periph1, periph2;
if (is_cpu_type(MXC_CPU_MX6SX))
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
return;
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs

6
arch/arm/imx-common/cpu.c
View File

@@ -122,6 +122,10 @@ unsigned imx_ddr_size(void)
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_MX6QP:
return "6QP"; /* Quad-Plus version of the mx6 */
case MXC_CPU_MX6DP:
return "6DP"; /* Dual-Plus version of the mx6 */
case MXC_CPU_MX6Q:
return "6Q"; /* Quad-core version of the mx6 */
case MXC_CPU_MX6D:
@@ -134,6 +138,8 @@ const char *get_imx_type(u32 imxtype)
return "6SL"; /* Solo-Lite version of the mx6 */
case MXC_CPU_MX6SX:
return "6SX"; /* SoloX version of the mx6 */
case MXC_CPU_MX6UL:
return "6UL"; /* Ultra-Lite version of the mx6 */
case MXC_CPU_MX51:
return "51";
case MXC_CPU_MX53:

8
arch/arm/imx-common/timer.c
View File

@@ -45,7 +45,8 @@ static inline int gpt_has_clk_source_osc(void)
#if defined(CONFIG_MX6)
if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
(soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
is_cpu_type(MXC_CPU_MX6UL))
return 1;
return 0;
@@ -103,10 +104,11 @@ int timer_init(void)
if (gpt_has_clk_source_osc()) {
i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
/* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
/* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
if (is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO) ||
is_cpu_type(MXC_CPU_MX6SX)) {
is_cpu_type(MXC_CPU_MX6SX) ||
is_cpu_type(MXC_CPU_MX6UL)) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */

5
arch/arm/include/asm/arch-imx/cpu.h
View File

@@ -10,8 +10,11 @@
#define MXC_CPU_MX6DL 0x61
#define MXC_CPU_MX6SX 0x62
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6D 0x64
#define MXC_CPU_MX6UL 0x64
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
#define MXC_CPU_MX6D 0x67
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
#define CS0_128 0
#define CS0_64M_CS1_64M 1

1
arch/arm/include/asm/arch-mx6/clock.h
View File

@@ -57,7 +57,6 @@ void hab_caam_clock_enable(unsigned char enable);
void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
void enable_uart_clk(unsigned char enable);
int enable_cspi_clock(unsigned char enable, unsigned spi_num);
int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
int enable_sata_clock(void);
void disable_sata_clock(void);

139
arch/arm/include/asm/arch-mx6/crm_regs.h
View File

@@ -110,6 +110,7 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCR_RBC_EN (1 << 27)
#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
/* CCR_WB does not exist on i.MX6SX/UL */
#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
#define MXC_CCM_CCR_COSC_EN (1 << 12)
@@ -123,6 +124,8 @@ struct mxc_ccm_reg {
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
/* Exists on i.MX6QP */
#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18)
/* Define the bits in register CSR */
#define MXC_CCM_CSR_COSC_READY (1 << 5)
@@ -148,12 +151,11 @@ struct mxc_ccm_reg {
/* Define the bits in register CBCDR */
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
#ifndef CONFIG_MX6SX
/* MMDC_CH0 not exists on i.MX6SX */
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
#endif
#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
@@ -176,7 +178,7 @@ struct mxc_ccm_reg {
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
#ifndef CONFIG_MX6SX
@@ -195,26 +197,25 @@ struct mxc_ccm_reg {
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
#ifndef CONFIG_MX6SX
#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
#endif
/* Exists on i.MX6QP */
#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1)
/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
#ifdef CONFIG_MX6SX
/* QSPI1 exist on i.MX6SX/UL */
#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
#else
#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
#endif
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
/* CSCMR1_GPMI/BCH exist on i.MX6UL */
#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19)
#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
@@ -225,14 +226,13 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
#ifdef CONFIG_MX6SX
/* QSPI1 exist on i.MX6SX/UL */
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
#endif
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
#endif
#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
/* Define the bits in register CSCMR2 */
@@ -244,21 +244,24 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
#ifdef CONFIG_MX6SX
/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
#else
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
#endif
/* Define the bits in register CSCDR1 */
#ifndef CONFIG_MX6SX
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
#endif
/* CSCDR1_GPMI/BCH exist on i.MX6UL */
#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19)
#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
@@ -273,16 +276,10 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
#endif
#ifdef CONFIG_MX6SL
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
#else
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
#ifdef CONFIG_MX6SX
#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
#endif
#endif
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* UART_CLK_SEL exists on i.MX6SL/SX/QP */
#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
/* Define the bits in register CS1CDR */
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
@@ -299,7 +296,7 @@ struct mxc_ccm_reg {
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
/* Define the bits in register CS2CDR */
#ifdef CONFIG_MX6SX
/* QSPI2 on i.MX6SX */
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
@@ -309,17 +306,34 @@ struct mxc_ccm_reg {
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
#else
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
#endif
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \
((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \
((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \
((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \
MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
@@ -384,6 +398,9 @@ struct mxc_ccm_reg {
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18)
/* All IPU2_DI1 are LCDIF1 on MX6SX */
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
@@ -544,10 +561,9 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
#ifndef CONFIG_MX6SX
#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
#endif
/* CCGR1_ENET does not exist on i.MX6SX/UL */
#define MXC_CCM_CCGR1_ENET_OFFSET 10
#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET)
#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
@@ -618,21 +634,21 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
#endif
#ifdef CONFIG_MX6SX
/* Exist on i.MX6SX */
#define MXC_CCM_CCGR3_M4_OFFSET 2
#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
#define MXC_CCM_CCGR3_ENET_OFFSET 4
#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
#define MXC_CCM_CCGR3_QSPI_OFFSET 14
#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
#else
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
#endif
#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
@@ -641,15 +657,22 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
#ifdef CONFIG_MX6SX
/* QSPI1 exists on i.MX6SX/UL */
#define MXC_CCM_CCGR3_QSPI1_OFFSET 14
#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
#else
#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
#endif
/* A7_CLKDIV/WDOG1 on i.MX6UL */
#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16
#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18
#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
#define MXC_CCM_CCGR3_MLB_OFFSET 18
#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
@@ -662,8 +685,16 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
/* AXI on i.MX6UL */
#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28
#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
/* GPIO4 on i.MX6UL */
#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30
#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
#ifndef CONFIG_MX6SX
#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
@@ -671,13 +702,11 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR4_PCIE_OFFSET 0
#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
#ifdef CONFIG_MX6SX
/* QSPI2 on i.MX6SX */
#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
#else
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
#endif
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
@@ -728,19 +757,28 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
#endif
/* PRG_CLK0 exists on i.MX6QP */
#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24)
#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
/* GPMI/BCH on i.MX6UL */
#define MXC_CCM_CCGR6_BCH_OFFSET 6
#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET)
#define MXC_CCM_CCGR6_GPMI_OFFSET 8
#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET)
#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
#ifdef CONFIG_MX6SX
/* The following *CCGR6* exist only i.MX6SX */
#define MXC_CCM_CCGR6_PWM8_OFFSET 16
#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
#define MXC_CCM_CCGR6_VADC_OFFSET 20
@@ -755,10 +793,9 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
#define MXC_CCM_CCGR6_PWM7_OFFSET 30
#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
#else
/* The two does not exist on i.MX6SX */
#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
#endif
#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
#define BP_ANADIG_PLL_SYS_RSVD0 20

85
arch/arm/include/asm/arch-mx6/hab.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*
@@ -23,24 +23,68 @@ enum hab_status {
/* Security Configuration definitions */
enum hab_config {
HAB_CFG_RETURN = 0x33, /**< Field Return IC */
HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */
HAB_CFG_CLOSED = 0xcc /**< Secure IC */
HAB_CFG_RETURN = 0x33, /* < Field Return IC */
HAB_CFG_OPEN = 0xf0, /* < Non-secure IC */
HAB_CFG_CLOSED = 0xcc /* < Secure IC */
};
/* State definitions */
enum hab_state {
HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */
HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */
HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */
HAB_STATE_TRUSTED = 0x99, /**< Trusted state */
HAB_STATE_SECURE = 0xaa, /**< Secure state */
HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */
HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */
HAB_STATE_NONE = 0xf0, /**< No security state machine */
HAB_STATE_INITIAL = 0x33, /* Initialising state (transitory) */
HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */
HAB_STATE_NONSECURE = 0x66, /* Non-secure state */
HAB_STATE_TRUSTED = 0x99, /* Trusted state */
HAB_STATE_SECURE = 0xaa, /* Secure state */
HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
HAB_STATE_NONE = 0xf0, /* No security state machine */
HAB_STATE_MAX
};
enum hab_reason {
HAB_RSN_ANY = 0x00, /* Match any reason */
HAB_ENG_FAIL = 0x30, /* Engine failure */
HAB_INV_ADDRESS = 0x22, /* Invalid address: access denied */
HAB_INV_ASSERTION = 0x0c, /* Invalid assertion */
HAB_INV_CALL = 0x28, /* Function called out of sequence */
HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
HAB_INV_COMMAND = 0x06, /* Invalid command: command malformed */
HAB_INV_CSF = 0x11, /* Invalid csf */
HAB_INV_DCD = 0x27, /* Invalid dcd */
HAB_INV_INDEX = 0x0f, /* Invalid index: access denied */
HAB_INV_IVT = 0x05, /* Invalid ivt */
HAB_INV_KEY = 0x1d, /* Invalid key */
HAB_INV_RETURN = 0x1e, /* Failed callback function */
HAB_INV_SIGNATURE = 0x18, /* Invalid signature */
HAB_INV_SIZE = 0x17, /* Invalid data size */
HAB_MEM_FAIL = 0x2e, /* Memory failure */
HAB_OVR_COUNT = 0x2b, /* Expired poll count */
HAB_OVR_STORAGE = 0x2d, /* Exhausted storage region */
HAB_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */
HAB_UNS_COMMAND = 0x03, /* Unsupported command */
HAB_UNS_ENGINE = 0x0a, /* Unsupported engine */
HAB_UNS_ITEM = 0x24, /* Unsupported configuration item */
HAB_UNS_KEY = 0x1b, /* Unsupported key type/parameters */
HAB_UNS_PROTOCOL = 0x14, /* Unsupported protocol */
HAB_UNS_STATE = 0x09, /* Unsuitable state */
HAB_RSN_MAX
};
enum hab_context {
HAB_CTX_ANY = 0x00, /* Match any context */
HAB_CTX_FAB = 0xff, /* Event logged in hab_fab_test() */
HAB_CTX_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */
HAB_CTX_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */
HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
HAB_CTX_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */
HAB_CTX_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */
HAB_CTX_COMMAND = 0xc0, /* Event logged executing csf/dcd command */
HAB_CTX_AUT_DAT = 0xdb, /* Authenticated data block */
HAB_CTX_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */
HAB_CTX_EXIT = 0xee, /* Event logged in hab_rvt.exit() */
HAB_CTX_MAX
};
/*Function prototype description*/
typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
uint8_t* , size_t*);
@@ -53,6 +97,22 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
typedef void hapi_clock_init_t(void);
#define HAB_ENG_ANY 0x00 /* Select first compatible engine */
#define HAB_ENG_SCC 0x03 /* Security controller */
#define HAB_ENG_RTIC 0x05 /* Run-time integrity checker */
#define HAB_ENG_SAHARA 0x06 /* Crypto accelerator */
#define HAB_ENG_CSU 0x0a /* Central Security Unit */
#define HAB_ENG_SRTC 0x0c /* Secure clock */
#define HAB_ENG_DCP 0x1b /* Data Co-Processor */
#define HAB_ENG_CAAM 0x1d /* CAAM */
#define HAB_ENG_SNVS 0x1e /* Secure Non-Volatile Storage */
#define HAB_ENG_OCOTP 0x21 /* Fuse controller */
#define HAB_ENG_DTCP 0x22 /* DTCP co-processor */
#define HAB_ENG_ROM 0x36 /* Protected ROM area */
#define HAB_ENG_HDCP 0x24 /* HDCP co-processor */
#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
#define HAB_ENG_SW 0xff /* Software engine */
#ifdef CONFIG_MX6SX
#define HAB_RVT_BASE 0x00000100
#else
@@ -73,6 +133,7 @@ typedef void hapi_clock_init_t(void);
#define HAB_CID_ROM 0 /**< ROM Caller ID */
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
/* ----------- end of HAB API updates ------------*/
#endif

64
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@@ -9,7 +9,11 @@
#define ARCH_MXC
#ifdef CONFIG_MX6UL
#define CONFIG_SYS_CACHELINE_SIZE 64
#else
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
@@ -19,7 +23,7 @@
#define GPU_2D_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
#elif CONFIG_MX6SX
#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00107FFF
#define GPU_ARB_BASE_ADDR 0x01800000
@@ -28,10 +32,6 @@
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
#else
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
@@ -52,13 +52,13 @@
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV2_BASE_ADDR 0x00D00000
#else
#define GPV2_BASE_ADDR 0x00200000
#endif
#ifdef CONFIG_MX6SX
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000
@@ -87,15 +87,21 @@
#define AIPS1_ARB_END_ADDR 0x020FFFFF
#define AIPS2_ARB_BASE_ADDR 0x02100000
#define AIPS2_ARB_END_ADDR 0x021FFFFF
#ifdef CONFIG_MX6SX
/* AIPS3 only on i.MX6SX */
#define AIPS3_ARB_BASE_ADDR 0x02200000
#define AIPS3_ARB_END_ADDR 0x022FFFFF
#ifdef CONFIG_MX6SX
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#define QSPI1_AMBA_BASE 0x70000000
#define QSPI1_AMBA_END 0x7FFFFFFF
#elif defined(CONFIG_MX6UL)
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#else
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
@@ -111,7 +117,7 @@
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
@@ -238,13 +244,16 @@
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
#ifdef CONFIG_MX6SL
/* i.MX6SL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#elif CONFIG_MX6SX
#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#ifdef CONFIG_MX6UL
#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#else
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
/* i.MX6SX */
#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#endif
/* i.MX6DQ/SDL */
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
@@ -257,22 +266,21 @@
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#endif
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
#ifdef CONFIG_MX6SX
#ifdef CONFIG_MX6UL
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#elif defined(CONFIG_MX6SX)
#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#else
#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#endif
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#ifdef CONFIG_MX6SX
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#else
#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#endif
#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
@@ -296,7 +304,6 @@
#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
@@ -308,12 +315,17 @@
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
#endif
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
/* only for i.MX6SX/UL */
#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20
#ifndef CONFIG_MX6SX
#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define IRAM_SIZE 0x00040000
#else
#define IRAM_SIZE 0x00020000
@@ -451,7 +463,7 @@ struct src {
struct iomuxc {
#ifdef CONFIG_MX6SX
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
u8 reserved[0x4000];
#endif
u32 gpr[14];
@@ -577,7 +589,7 @@ struct cspi_regs {
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
@@ -661,7 +673,7 @@ struct fuse_bank1_regs {
u32 rsvd7[3];
};
#ifdef CONFIG_MX6SX
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
@@ -674,7 +686,9 @@ struct fuse_bank4_regs {
u32 mac_addr2;
u32 rsvd4[7];
u32 gp1;
u32 rsvd5[7];
u32 rsvd5[3];
u32 gp2;
u32 rsvd6[3];
};
#else
struct fuse_bank4_regs {

45
arch/arm/include/asm/arch-mx6/mx6-ddr.h
View File

@@ -16,7 +16,11 @@
#ifdef CONFIG_MX6SX
#include "mx6sx-ddr.h"
#else
#ifdef CONFIG_MX6UL
#include "mx6ul-ddr.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6UL */
#endif /* CONFIG_MX6SX */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
@@ -62,6 +66,44 @@ struct mmdc_p_regs {
u32 mpmur0;
};
#define MX6UL_IOM_DDR_BASE 0x020e0200
struct mx6ul_iomux_ddr_regs {
u32 res1[17];
u32 dram_dqm0;
u32 dram_dqm1;
u32 dram_ras;
u32 dram_cas;
u32 dram_cs0;
u32 dram_cs1;
u32 dram_sdwe_b;
u32 dram_odt0;
u32 dram_odt1;
u32 dram_sdba0;
u32 dram_sdba1;
u32 dram_sdba2;
u32 dram_sdcke0;
u32 dram_sdcke1;
u32 dram_sdclk_0;
u32 dram_sdqs0;
u32 dram_sdqs1;
u32 dram_reset;
};
#define MX6UL_IOM_GRP_BASE 0x020e0400
struct mx6ul_iomux_grp_regs {
u32 res1[36];
u32 grp_addds;
u32 grp_ddrmode_ctl;
u32 grp_b0ds;
u32 grp_ddrpk;
u32 grp_ctlds;
u32 grp_b1ds;
u32 grp_ddrhys;
u32 grp_ddrpke;
u32 grp_ddrmode;
u32 grp_ddr_type;
};
#define MX6SX_IOM_DDR_BASE 0x020e0200
struct mx6sx_iomux_ddr_regs {
u32 res1[59];
@@ -290,6 +332,9 @@ void mx6sdl_dram_iocfg(unsigned width,
void mx6sx_dram_iocfg(unsigned width,
const struct mx6sx_iomux_ddr_regs *,
const struct mx6sx_iomux_grp_regs *);
void mx6ul_dram_iocfg(unsigned width,
const struct mx6ul_iomux_ddr_regs *,
const struct mx6ul_iomux_grp_regs *);
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,

2
arch/arm/include/asm/arch-mx6/mx6-pins.h
View File

@@ -37,6 +37,8 @@ enum {
#include "mx6sl_pins.h"
#elif defined(CONFIG_MX6SX)
#include "mx6sx_pins.h"
#elif defined(CONFIG_MX6UL)
#include "mx6ul_pins.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6Q */

45
arch/arm/include/asm/arch-mx6/mx6ul-ddr.h Normal file
View File

@@ -0,0 +1,45 @@
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6UL_DDR_H__
#define __ASM_ARCH_MX6UL_DDR_H__
#ifndef CONFIG_MX6UL
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_DQM0 0x020e0244
#define MX6_IOM_DRAM_DQM1 0x020e0248
#define MX6_IOM_DRAM_RAS 0x020e024c
#define MX6_IOM_DRAM_CAS 0x020e0250
#define MX6_IOM_DRAM_CS0 0x020e0254
#define MX6_IOM_DRAM_CS1 0x020e0258
#define MX6_IOM_DRAM_SDWE_B 0x020e025c
#define MX6_IOM_DRAM_SDODT0 0x020e0260
#define MX6_IOM_DRAM_SDODT1 0x020e0264
#define MX6_IOM_DRAM_SDBA0 0x020e0268
#define MX6_IOM_DRAM_SDBA1 0x020e026c
#define MX6_IOM_DRAM_SDBA2 0x020e0270
#define MX6_IOM_DRAM_SDCKE0 0x020e0274
#define MX6_IOM_DRAM_SDCKE1 0x020e0278
#define MX6_IOM_DRAM_SDCLK_0 0x020e027c
#define MX6_IOM_DRAM_SDQS0 0x020e0280
#define MX6_IOM_DRAM_SDQS1 0x020e0284
#define MX6_IOM_DRAM_RESET 0x020e0288
#define MX6_IOM_GRP_ADDDS 0x020e0490
#define MX6_IOM_DDRMODE_CTL 0x020e0494
#define MX6_IOM_GRP_B0DS 0x020e0498
#define MX6_IOM_GRP_DDRPK 0x020e049c
#define MX6_IOM_GRP_CTLDS 0x020e04a0
#define MX6_IOM_GRP_B1DS 0x020e04a4
#define MX6_IOM_GRP_DDRHYS 0x020e04a8
#define MX6_IOM_GRP_DDRPKE 0x020e04ac
#define MX6_IOM_GRP_DDRMODE 0x020e04b0
#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4
#endif /*__ASM_ARCH_MX6SX_DDR_H__ */

1065
arch/arm/include/asm/arch-mx6/mx6ul_pins.h Normal file
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/include/asm/arch-mx6/sys_proto.h
View File

@@ -30,9 +30,7 @@ const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
void set_chipselect_size(int const);
#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \
is_cpu_type(MXC_CPU_MX6D)) && \
(soc_rev() >= CHIP_REV_2_0))
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
/*
* Initializes on-chip ethernet controllers.

3
arch/arm/include/asm/arch-vf610/crm_regs.h
View File

@@ -207,6 +207,7 @@ struct anadig_reg {
#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
@@ -216,6 +217,8 @@ struct anadig_reg {
#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
#define CCM_CCGR10_NFC_CTRL_MASK 0x3
#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12)
#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14)
#define ANADIG_PLL7_CTRL_BYPASS (1 << 16)
#define ANADIG_PLL7_CTRL_ENABLE (1 << 13)

3
arch/arm/include/asm/arch-vf610/imx-regs.h
View File

@@ -75,6 +75,9 @@
#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
#define I2C2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00067000)
#define I2C3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E6000)
#define I2C4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E7000)
#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)

11
arch/arm/include/asm/arch-vf610/iomux-vf610.h
View File

@@ -20,7 +20,8 @@
#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \
PAD_CTL_INPUT_DIFFERENTIAL)
#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | \
PAD_CTL_OBE_IBE_ENABLE)
#define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \
PAD_CTL_OBE_IBE_ENABLE)
@@ -110,6 +111,8 @@ enum {
VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_PTA22__I2C2_SCL = IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL),
VF610_PAD_PTA23__I2C2_SDA = IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL),
VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
@@ -146,10 +149,10 @@ enum {
VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD19__NF_IO3 = IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD17__NF_IO1 = IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTD16__NF_IO0 = IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),

6
arch/arm/include/asm/imx-common/iomux-v3.h
View File

@@ -98,7 +98,11 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_ODE (1 << 11)
#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
#define PAD_CTL_SPEED_LOW (0 << 6)
#else
#define PAD_CTL_SPEED_LOW (1 << 6)
#endif
#define PAD_CTL_SPEED_MED (2 << 6)
#define PAD_CTL_SPEED_HIGH (3 << 6)
@@ -127,6 +131,8 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_SRE (1 << 11)
#define PAD_CTL_ODE (1 << 10)
#define PAD_CTL_DSE_150ohm (1 << 6)
#define PAD_CTL_DSE_50ohm (3 << 6)
#define PAD_CTL_DSE_25ohm (6 << 6)