stm32mp1: pwr: use the last binding for pwr

Update the driver to use the latest binding from kernel v5.5-rc1:
no more use syscon or regmap to access to pwr register and
only one pwr_regulators node with the compatibility "st,stm32mp1,pwr-reg"
is available.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

arch/arm/dts/stm32mp157-u-boot.dtsi

@@ -128,7 +128,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&pwr {
+&pwr_regulators {
 	u-boot,dm-pre-reloc;
 };
 

arch/arm/dts/stm32mp157a-avenger96.dts

@@ -282,11 +282,9 @@
 	status = "okay";
 };
 
-&pwr {
+&pwr_regulators {
-	pwr-regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;
-	};
 };
 
 &rng1 {

arch/arm/dts/stm32mp157a-dk1.dts

@@ -397,11 +397,9 @@
 	status = "okay";
 };
 
-&pwr {
+&pwr_regulators {
-	pwr-regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;
-	};
 };
 
 &rng1 {

arch/arm/dts/stm32mp157c-ed1.dts

@@ -263,11 +263,9 @@
 	status = "okay";
 };
 
-&pwr {
+&pwr_regulators {
-	pwr-regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;
-	};
 };
 
 &rng1 {

arch/arm/dts/stm32mp157c.dtsi

@@ -1110,18 +1110,9 @@
 			#reset-cells = <1>;
 		};
 
-		pwr: pwr@50001000 {
+		pwr_regulators: pwr@50001000 {
-			compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
-			reg = <0x50001000 0x400>;
-			system-power-controller;
-			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-			st,sysrcc = <&rcc>;
-			clocks = <&rcc PLL2_R>;
-			clock-names = "phyclk";
-
-			pwr-regulators {
 			compatible = "st,stm32mp1,pwr-reg";
-				st,tzcr = <&rcc 0x0 0x1>;
+			reg = <0x50001000 0x10>;
 
 			reg11: reg11 {
 				regulator-name = "reg11";
@@ -1141,7 +1132,6 @@
 				regulator-max-microvolt = <3300000>;
 			};
 		};
-		};
 
 		exti: interrupt-controller@5000d000 {
 			compatible = "st,stm32mp1-exti", "syscon";

arch/arm/dts/stm32mp15xx-dhcom.dtsi

@@ -217,11 +217,9 @@
 	status = "okay";
 };
 
-&pwr {
+&pwr_regulators {
-	pwr-regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;
-	};
 };
 
 &qspi {

arch/arm/mach-stm32mp/include/mach/stm32.h

@@ -37,7 +37,6 @@
 /* enumerated used to identify the SYSCON driver instance */
 enum {
 	STM32MP_SYSCON_UNKNOWN,
-	STM32MP_SYSCON_PWR,
 	STM32MP_SYSCON_SYSCFG,
 };
 

arch/arm/mach-stm32mp/pwr_regulator.c

@@ -6,8 +6,8 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <regmap.h>
 #include <syscon.h>
+#include <asm/io.h>
 #include <dm/device_compat.h>
 #include <linux/err.h>
 #include <power/pmic.h>
@@ -28,7 +28,7 @@ struct stm32mp_pwr_reg_info {
 };
 
 struct stm32mp_pwr_priv {
-	struct regmap *regmap;
+	fdt_addr_t base;
 };
 
 static int stm32mp_pwr_write(struct udevice *dev, uint reg,
@@ -40,7 +40,9 @@ static int stm32mp_pwr_write(struct udevice *dev, uint reg,
 	if (len != 4)
 		return -EINVAL;
 
-	return regmap_write(priv->regmap, STM32MP_PWR_CR3, val);
+	writel(val, priv->base + STM32MP_PWR_CR3);
+
+	return 0;
 }
 
 static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
@@ -51,21 +53,18 @@ static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
 	if (len != 4)
 		return -EINVAL;
 
-	return regmap_read(priv->regmap, STM32MP_PWR_CR3, (u32 *)buff);
+	*(u32 *)buff = readl(priv->base + STM32MP_PWR_CR3);
+
+	return 0;
 }
 
 static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
 {
 	struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
-	struct regmap *regmap;
 
-	regmap = syscon_get_regmap_by_driver_data(STM32MP_SYSCON_PWR);
+	priv->base = dev_read_addr(dev);
-	if (IS_ERR(regmap)) {
+	if (priv->base == FDT_ADDR_T_NONE)
-		pr_err("%s: unable to find regmap (%ld)\n", __func__,
+		return -EINVAL;
-		       PTR_ERR(regmap));
-		return PTR_ERR(regmap);
-	}
-	priv->regmap = regmap;
 
 	return 0;
 }

arch/arm/mach-stm32mp/syscon.c

@@ -9,7 +9,6 @@
 #include <asm/arch/stm32.h>
 
 static const struct udevice_id stm32mp_syscon_ids[] = {
-	{ .compatible = "st,stm32mp1-pwr", .data = STM32MP_SYSCON_PWR },
 	{ .compatible = "st,stm32mp157-syscfg",
 	  .data = STM32MP_SYSCON_SYSCFG },
 	{ }