mirror of
				https://xff.cz/git/u-boot/
				synced 2025-10-31 10:26:10 +01:00 
			
		
		
		
	arm: stm32mp: correct the ALIGN macro usage
Correct the ALIGN macro usage in mmu_set_region_dcache_behaviour
call: the address must use ALIGN_DOWN and size can use ALIGN macro.
With STM32_SYSRAM_BASE=0x2FFC0000 and MMU_SECTION_SIZE=0x100000 for
STM32MP15x the computed address was 30000000 instead of 2ff00000.
Fixes: 43fe9d2fda ("stm32mp1: mmu_set_region_dcache_behaviour")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
			
			
This commit is contained in:
		| @@ -226,8 +226,8 @@ static void early_enable_caches(void) | |||||||
|  |  | ||||||
| 	if (IS_ENABLED(CONFIG_SPL_BUILD)) | 	if (IS_ENABLED(CONFIG_SPL_BUILD)) | ||||||
| 		mmu_set_region_dcache_behaviour( | 		mmu_set_region_dcache_behaviour( | ||||||
| 			ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), | 			ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), | ||||||
| 			round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), | 			ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), | ||||||
| 			DCACHE_DEFAULT_OPTION); | 			DCACHE_DEFAULT_OPTION); | ||||||
| 	else | 	else | ||||||
| 		mmu_set_region_dcache_behaviour(STM32_DDR_BASE, | 		mmu_set_region_dcache_behaviour(STM32_DDR_BASE, | ||||||
|   | |||||||
		Reference in New Issue
	
	Block a user