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mips: Remove duplicate newlines

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Drop all duplicate newlines. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
2024-07-13 15:19:25 +02:00
committed by Tom Rini
parent 16ede53925
commit 76964e3f6d
6 changed files with 0 additions and 12 deletions
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1
arch/mips/include/asm/io.h
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@@ -485,7 +485,6 @@ BUILDSTRING(q, u64)
#define outsq outsq #define outsq outsq
#endif #endif
#ifdef CONFIG_CPU_CAVIUM_OCTEON #ifdef CONFIG_CPU_CAVIUM_OCTEON
#define mmiowb() wmb() #define mmiowb() wmb()
#else #else

1
arch/mips/include/asm/isa-rev.h
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@@ -20,5 +20,4 @@
#define MIPS_ISA_REV 0 #define MIPS_ISA_REV 0
#endif #endif
#endif /* __MIPS_ASM_ISA_REV_H__ */ #endif /* __MIPS_ASM_ISA_REV_H__ */

6
arch/mips/include/asm/mipsregs.h
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@@ -125,7 +125,6 @@
*/ */
#define CP0_TX39_CACHE $7 #define CP0_TX39_CACHE $7
/* Generic EntryLo bit definitions */ /* Generic EntryLo bit definitions */
#define ENTRYLO_G (_ULCAST_(1) << 0) #define ENTRYLO_G (_ULCAST_(1) << 0)
#define ENTRYLO_V (_ULCAST_(1) << 1) #define ENTRYLO_V (_ULCAST_(1) << 1)
@@ -987,7 +986,6 @@
#define CP1_FENR $28 #define CP1_FENR $28
#define CP1_STATUS $31 #define CP1_STATUS $31
/* /*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/ */
@@ -1102,7 +1100,6 @@
#define FPU_CSR_RU 0x2 /* towards +Infinity */ #define FPU_CSR_RU 0x2 /* towards +Infinity */
#define FPU_CSR_RD 0x3 /* towards -Infinity */ #define FPU_CSR_RD 0x3 /* towards -Infinity */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/* /*
@@ -1261,7 +1258,6 @@ static inline void tlbinvf(void)
".set pop"); ".set pop");
} }
/* /*
* Functions to access the R10000 performance counters. These are basically * Functions to access the R10000 performance counters. These are basically
* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
@@ -1307,7 +1303,6 @@ do { \
: "r" (val), "i" (counter)); \ : "r" (val), "i" (counter)); \
} while (0) } while (0)
/* /*
* Macros to access the system control coprocessor * Macros to access the system control coprocessor
*/ */
@@ -2403,7 +2398,6 @@ do { \
mfhi3; \ mfhi3; \
}) })
#define mtlo0(x) \ #define mtlo0(x) \
({ \ ({ \
__asm__( \ __asm__( \

2
arch/mips/include/asm/pgtable-bits.h
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@@ -7,7 +7,6 @@
#ifndef _ASM_PGTABLE_BITS_H #ifndef _ASM_PGTABLE_BITS_H
#define _ASM_PGTABLE_BITS_H #define _ASM_PGTABLE_BITS_H
/* /*
* Note that we shift the lower 32bits of each EntryLo[01] entry * Note that we shift the lower 32bits of each EntryLo[01] entry
* 6 bits to the left. That way we can convert the PFN into the * 6 bits to the left. That way we can convert the PFN into the
@@ -189,7 +188,6 @@
* 32-bit, R2 or later: CCC D V G RI/R XI M A W P * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
*/ */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/* /*
* pte_to_entrylo converts a page table entry (PTE) into a Mips * pte_to_entrylo converts a page table entry (PTE) into a Mips

1
arch/mips/mach-ath79/qca953x/clk.c
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@@ -61,7 +61,6 @@ int get_clocks(void)
& QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1; & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
gd->cpu_clk = pll / div; gd->cpu_clk = pll / div;
val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG); val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
/* VCOOUT = XTAL * DIV_INT */ /* VCOOUT = XTAL * DIV_INT */
div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)

1
arch/mips/mach-octeon/include/mangle-port.h
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@@ -43,7 +43,6 @@ static inline bool __should_swizzle_addr(u64 p)
#endif /* __BIG_ENDIAN */ #endif /* __BIG_ENDIAN */
# define ioswabb(a, x) (x) # define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x) # define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (__should_swizzle_bits(a) ? le16_to_cpu(x) : x) # define ioswabw(a, x) (__should_swizzle_bits(a) ? le16_to_cpu(x) : x)