dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-09-25 20:41:16 +02:00
Code Issues Packages Projects Releases Wiki Activity

ddr: fsl: Impl. Erratum A008109

Browse Source 
Impl. erratum as descibed in errata doc.
Enable A008109 for T1040 and T1024

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Joakim Tjernlund
2019-11-20 17:07:34 +01:00
committed by Priyanka Jain
parent a0f47e012f
commit 73af094c84
3 changed files with 11 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@@ -1038,6 +1038,7 @@ config ARCH_T1040
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC111
@@ -1061,6 +1062,7 @@ config ARCH_T1042
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111 select SYS_FSL_ERRATUM_ESDHC111

3
drivers/ddr/fsl/Kconfig
View File

@@ -151,6 +151,9 @@ endmenu
config SYS_FSL_ERRATUM_A008378 config SYS_FSL_ERRATUM_A008378
bool bool
config SYS_FSL_ERRATUM_A008109
bool
config SYS_FSL_ERRATUM_A008511 config SYS_FSL_ERRATUM_A008511
bool bool

6
drivers/ddr/fsl/ctrl_regs.c
View File

@@ -2628,6 +2628,12 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
} }
#endif #endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008109
ddr->ddr_sdram_cfg_2 = ddr_in32(&ddr->ddr_sdram_cfg_2) | 0x800; /* DDR_SLOW */
ddr->debug[18] = ddr_in32(&ddrc->debug[18]) | 0x2;
ddr->debug[28] = 0x30000000;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
ddr_freq = get_ddr_freq(ctrl_num) / 1000000; ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);