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x86: Select advanced Intel code only if allowed

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At present most of the Intel-specific code is built on all devices, even
those which don't have software support for the features provided there.

This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does
not have the required features.

Add a new INTEL_SOC option to control this access. This must be selected
by SoCs that can support the required features.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
2021-02-23 05:35:42 -05:00
committed by Bin Meng
parent 049c4dc677
commit 736ecc643d
2 changed files with 16 additions and 0 deletions
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15
arch/x86/Kconfig
View File

@@ -1001,6 +1001,19 @@ config PCIEX_LENGTH_128MB
config PCIEX_LENGTH_64MB config PCIEX_LENGTH_64MB
bool bool
config INTEL_SOC
bool
help
This is enabled on Intel SoCs that can support various advanced
features such as power management (requiring asm/arch/pm.h), system
agent (asm/arch/systemagent.h) and an I/O map for ACPI
(asm/arch/iomap.h).
This cannot be selected in a defconfig file. It must be enabled by a
'select' in the SoC's Kconfig.
if INTEL_SOC
config INTEL_ACPIGEN config INTEL_ACPIGEN
bool "Support ACPI table generation for Intel SoCs" bool "Support ACPI table generation for Intel SoCs"
depends on ACPIGEN depends on ACPIGEN
@@ -1032,4 +1045,6 @@ config INTEL_GMA_SWSMISCI
Select this option for Atom-based platforms which use the SWSMISCI Select this option for Atom-based platforms which use the SWSMISCI
register (0xe0) rather than the SWSCI register (0xe8). register (0xe0) rather than the SWSCI register (0xe8).
endif # INTEL_SOC
endmenu endmenu

1
arch/x86/cpu/apollolake/Kconfig
View File

@@ -9,6 +9,7 @@ config INTEL_APOLLOLAKE
select HAVE_FSP select HAVE_FSP
select ARCH_MISC_INIT select ARCH_MISC_INIT
select USE_CAR select USE_CAR
select INTEL_SOC
select INTEL_PMC select INTEL_PMC
select TPL_X86_TSC_TIMER_NATIVE select TPL_X86_TSC_TIMER_NATIVE
select SPL_PCH_SUPPORT select SPL_PCH_SUPPORT