dany/u-boot-megous
1
0
Fork 0
mirror of https://xff.cz/git/u-boot/ synced 2025-09-02 09:12:08 +02:00
Code Issues Packages Projects Releases Wiki Activity

arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig

Browse Source 
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan
2017-04-05 17:32:51 +08:00
committed by Marek Vasut
parent e11b5e8d6e
commit 707cd012e2
6 changed files with 12 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-socfpga/Kconfig
View File

@@ -43,6 +43,7 @@ config TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_GEN5 config TARGET_SOCFPGA_GEN5
bool bool
select ALTERA_SDRAM
choice choice
prompt "Altera SOCFPGA board select" prompt "Altera SOCFPGA board select"

2
drivers/Kconfig
View File

@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
source "drivers/crypto/Kconfig" source "drivers/crypto/Kconfig"
source "drivers/ddr/Kconfig"
source "drivers/demo/Kconfig" source "drivers/demo/Kconfig"
source "drivers/ddr/fsl/Kconfig" source "drivers/ddr/fsl/Kconfig"

1
drivers/ddr/Kconfig Normal file
View File

@@ -0,0 +1 @@
source "drivers/ddr/altera/Kconfig"

5
drivers/ddr/altera/Kconfig Normal file
View File

@@ -0,0 +1,5 @@
config ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver"
depends on TARGET_SOCFPGA_GEN5
help
Enable DDR SDRAM controller for the SoCFPGA devices.

4
drivers/ddr/altera/Makefile
View File

@@ -8,4 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o ifdef CONFIG_ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
endif

5
include/configs/socfpga_common.h
View File

@@ -71,11 +71,6 @@
#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
* SDRAM controller
*/
#define CONFIG_ALTERA_SDRAM
/* /*
* EPCS/EPCQx1 Serial Flash Controller * EPCS/EPCQx1 Serial Flash Controller
*/ */