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dm: pci: Use a 1:1 mapping for bus <-> phy addresses

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If U-Boot gets used as coreboot payload all pci resources got
assigned by coreboot. If a dts without any pci ranges gets used
the dm is not able to access pci device memory. To get things
working make use of a 1:1 mapping for bus <-> phy addresses.

This change makes it possible to get the e1000 U-Boot driver
working on a sandybridge device where U-Boot is used as coreboot
payload.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Christian Gmeiner
2018-06-10 06:25:06 -07:00
committed by Bin Meng
parent f2825f6ec0
commit 6f95d89c71
1 changed files with 10 additions and 0 deletions
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10
drivers/pci/pci-uclass.c
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@@ -1182,6 +1182,11 @@ static int _dm_pci_bus_to_phys(struct udevice *ctlr,
struct pci_region *res;
int i;
if (hose->region_count == 0) {
*pa = bus_addr;
return 0;
}
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
@@ -1245,6 +1250,11 @@ int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
ctlr = pci_get_controller(dev);
hose = dev_get_uclass_priv(ctlr);
if (hose->region_count == 0) {
*ba = phys_addr;
return 0;
}
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];