net, qe: add DM support for QE UEC ethernet

add DM/DTS support for the UEC ethernet on QUICC Engine
Block.

Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com>

Series-changes: 3
- revert:
  commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled")
  as now qe works with DM and DM_ETH support.
- fix mailaddress from Holger

Series-changes: 2
- add comments from Qiang Zhao:
  - add device node documentation
  - I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c
    because using drivers/net/fsl_mdio.c leads in none existent
    udevice mdio@3320
    instead boards with DM ETH support should use now this
    driver.
- remove RFC tag

Commit-notes:

- I let the old none DM based implementation in code
  so boards should work with old implementation.
  This Code should be removed if all boards are converted
  to DM/DTS.

- add the DM based qe uec driver under drivers/net/qe

- Therefore copied the files uccf.c uccf.h uec.h from
  drivers/qe. So there are a lot of Codingstyle problems
  currently. I fix them in next version if this RFC
  patch is OK or it needs some changes.

- The dm based driver code is now under drivers/net/qe/dm_qe_uec.c
  Used a lot of functions from drivers/qe/uec.c

- seperated the PHY specific code into seperate file
  drivers/net/qe/dm_qe_uec_phy.c

END

doc/device-tree-bindings/soc/fsl/cpm_qe/qe/ucc.txt

@@ -0,0 +1,53 @@
+* UCC (Unified Communications Controllers)
+
+Required properties:
+- compatible : ucc_geth
+- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
+- reg : Offset and length of the register set for the device
+- rx-clock-name: the UCC receive clock source
+  "none": clock source is disabled
+  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
+  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
+- tx-clock-name: the UCC transmit clock source
+  "none": clock source is disabled
+  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
+  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
+The following two properties are deprecated.  rx-clock has been replaced
+with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
+Drivers that currently use the deprecated properties should continue to
+do so, in order to support older device trees, but they should be updated
+to check for the new properties first.
+- rx-clock : represents the UCC receive clock source.
+  0x00 : clock source is disabled;
+  0x1~0x10 : clock source is BRG1~BRG16 respectively;
+  0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+- tx-clock: represents the UCC transmit clock source;
+  0x00 : clock source is disabled;
+  0x1~0x10 : clock source is BRG1~BRG16 respectively;
+  0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+- phy-handle : The phandle for the PHY connected to this controller.
+- phy-connection-type : a string naming the controller/PHY interface type,
+  i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
+  Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
+  "tbi", or "rtbi".
+- pio-handle : The phandle for the Parallel I/O port configuration.
+
+Deprecated properties:
+- device-id : the ucc number(1-8), corresponding to UCCx in UM.
+    you should use cell-index
+
+Example:
+        ucc@2000 {
+                device_type = "network";
+                compatible = "ucc_geth";
+                cell-index = <1>;
+                reg = <2000 200>;
+                interrupts = <a0 0>;
+                interrupt-parent = <700>;
+                mac-address = [ 00 04 9f 00 23 23 ];
+                rx-clock = "none";
+                tx-clock = "clk9";
+                phy-handle = <212000>;
+                phy-connection-type = "gmii";
+                pio-handle = <140001>;
+        };