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arm: socfpga: Move Stratix 10 SDRAM driver to DM
Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan
committed by
Marek Vasut
Marek Vasut
parent
bc17990876
commit
6bf238a461
@@ -1,8 +1,8 @@
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config SPL_ALTERA_SDRAM
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bool "SoCFPGA DDR SDRAM driver in SPL"
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depends on SPL
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depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
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select RAM if TARGET_SOCFPGA_GEN5
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select SPL_RAM if TARGET_SOCFPGA_GEN5
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depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10
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select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
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select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
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help
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Enable DDR SDRAM controller for the SoCFPGA devices.
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@@ -5,17 +5,31 @@
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <div64.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <ram.h>
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#include <reset.h>
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#include "sdram_s10.h"
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#include <wait_bit.h>
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#include <asm/arch/firewall_s10.h>
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#include <asm/arch/sdram_s10.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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struct altera_sdram_priv {
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struct ram_info info;
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struct reset_ctl_bulk resets;
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};
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struct altera_sdram_platdata {
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void __iomem *hmc;
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void __iomem *ddr_sch;
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void __iomem *iomhc;
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};
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_system_manager *sysmgr_regs =
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@@ -51,25 +65,26 @@ u32 ddr_config[] = {
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DDR_CONFIG(1, 4, 10, 17),
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};
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static u32 hmc_readl(u32 reg)
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static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
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{
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return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg)));
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return readl(plat->iomhc + reg);
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}
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static u32 hmc_ecc_readl(u32 reg)
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static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
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{
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return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
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return readl(plat->hmc + reg);
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}
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static u32 hmc_ecc_writel(u32 data, u32 reg)
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static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
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u32 data, u32 reg)
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{
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return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
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return writel(data, plat->hmc + reg);
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}
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static u32 ddr_sch_writel(u32 data, u32 reg)
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static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
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u32 reg)
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{
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return writel(data,
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(void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg));
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return writel(data, plat->ddr_sch + reg);
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}
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int match_ddr_conf(u32 ddr_conf)
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@@ -83,37 +98,38 @@ int match_ddr_conf(u32 ddr_conf)
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return 0;
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}
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static int emif_clear(void)
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static int emif_clear(struct altera_sdram_platdata *plat)
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{
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hmc_ecc_writel(0, RSTHANDSHAKECTRL);
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hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
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return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
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return wait_for_bit_le32((const void *)(plat->hmc +
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RSTHANDSHAKESTAT),
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DDR_HMC_RSTHANDSHAKE_MASK,
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false, 1000, false);
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}
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static int emif_reset(void)
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static int emif_reset(struct altera_sdram_platdata *plat)
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{
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u32 c2s, s2c, ret;
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c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
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s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
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c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
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s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
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debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
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c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1),
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hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS));
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c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
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hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
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hmc_readl(plat, DRAMSTS));
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if (s2c && emif_clear()) {
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if (s2c && emif_clear(plat)) {
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printf("DDR: emif_clear() failed\n");
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return -1;
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}
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debug("DDR: Triggerring emif reset\n");
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hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
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hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
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/* if seq2core[3] = 0, we are good */
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ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
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ret = wait_for_bit_le32((const void *)(plat->hmc +
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RSTHANDSHAKESTAT),
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DDR_HMC_SEQ2CORE_INT_RESP_MASK,
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false, 1000, false);
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@@ -122,7 +138,7 @@ static int emif_reset(void)
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return ret;
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}
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ret = emif_clear();
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ret = emif_clear(plat);
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if (ret) {
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printf("DDR: emif_clear() failed\n");
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return ret;
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@@ -240,13 +256,37 @@ static void sdram_size_check(bd_t *bd)
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debug("DDR: SDRAM size check passed!\n");
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}
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/**
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* sdram_calculate_size() - Calculate SDRAM size
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*
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* Calculate SDRAM device size based on SDRAM controller parameters.
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* Size is specified in bytes.
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*/
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static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
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{
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u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
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phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
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DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
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size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
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DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
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return size;
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}
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/**
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* sdram_mmr_init_full() - Function to initialize SDRAM MMR
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*
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* Initialize the SDRAM MMR.
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*/
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int sdram_mmr_init_full(unsigned int unused)
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static int sdram_mmr_init_full(struct udevice *dev)
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{
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struct altera_sdram_platdata *plat = dev->platdata;
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struct altera_sdram_priv *priv = dev_get_priv(dev);
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u32 update_value, io48_value, ddrioctl;
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u32 i;
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int ret;
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@@ -303,19 +343,16 @@ int sdram_mmr_init_full(unsigned int unused)
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return -1;
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}
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/* release DDR scheduler from reset */
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socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
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/* Try 3 times to do a calibration */
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for (i = 0; i < 3; i++) {
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ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
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ret = wait_for_bit_le32((const void *)(plat->hmc +
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DDRCALSTAT),
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DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
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false);
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if (!ret)
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break;
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emif_reset();
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emif_reset(plat);
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}
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if (ret) {
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@@ -324,16 +361,16 @@ int sdram_mmr_init_full(unsigned int unused)
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}
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debug("DDR: Calibration success\n");
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u32 ctrlcfg0 = hmc_readl(CTRLCFG0);
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u32 ctrlcfg1 = hmc_readl(CTRLCFG1);
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u32 dramaddrw = hmc_readl(DRAMADDRW);
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u32 dramtim0 = hmc_readl(DRAMTIMING0);
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u32 caltim0 = hmc_readl(CALTIMING0);
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u32 caltim1 = hmc_readl(CALTIMING1);
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u32 caltim2 = hmc_readl(CALTIMING2);
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u32 caltim3 = hmc_readl(CALTIMING3);
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u32 caltim4 = hmc_readl(CALTIMING4);
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u32 caltim9 = hmc_readl(CALTIMING9);
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u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
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u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
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u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
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u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
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u32 caltim0 = hmc_readl(plat, CALTIMING0);
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u32 caltim1 = hmc_readl(plat, CALTIMING1);
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u32 caltim2 = hmc_readl(plat, CALTIMING2);
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u32 caltim3 = hmc_readl(plat, CALTIMING3);
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u32 caltim4 = hmc_readl(plat, CALTIMING4);
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u32 caltim9 = hmc_readl(plat, CALTIMING9);
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/*
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* Configure the DDR IO size [0xFFCFB008]
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@@ -349,12 +386,12 @@ int sdram_mmr_init_full(unsigned int unused)
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* bit[9:6] = Minor Release #
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* bit[14:10] = Major Release #
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*/
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update_value = hmc_readl(NIOSRESERVED0);
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hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL);
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ddrioctl = hmc_ecc_readl(DDRIOCTRL);
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update_value = hmc_readl(plat, NIOSRESERVED0);
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hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
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ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
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/* enable HPS interface to HMC */
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hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
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hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
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/* Set the DDR Configuration */
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io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
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@@ -365,10 +402,10 @@ int sdram_mmr_init_full(unsigned int unused)
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update_value = match_ddr_conf(io48_value);
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if (update_value)
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ddr_sch_writel(update_value, DDR_SCH_DDRCONF);
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ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
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/* Configure HMC dramaddrw */
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hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH);
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hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
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/*
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* Configure DDR timing
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@@ -392,7 +429,7 @@ int sdram_mmr_init_full(unsigned int unused)
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CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
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CALTIMING4_CFG_PCH_TO_VALID(caltim4));
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ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
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ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
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DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
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(update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
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(io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
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@@ -406,12 +443,12 @@ int sdram_mmr_init_full(unsigned int unused)
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DDR_SCH_DDRTIMING);
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/* Configure DDR mode [precharge = 0] */
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ddr_sch_writel(((ddrioctl ? 0 : 1) <<
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ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
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DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
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DDR_SCH_DDRMODE);
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/* Configure the read latency */
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ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
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ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
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DDR_READ_LATENCY_DELAY,
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DDR_SCH_READ_LATENCY);
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@@ -419,7 +456,7 @@ int sdram_mmr_init_full(unsigned int unused)
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* Configuring timing values concerning activate commands
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* [FAWBANK alway 1 because always 4 bank DDR]
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*/
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ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
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ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
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DDR_SCH_ACTIVATE_RRD_OFF) |
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(CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
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DDR_SCH_ACTIVATE_FAW_OFF) |
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@@ -431,7 +468,7 @@ int sdram_mmr_init_full(unsigned int unused)
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* Configuring timing values concerning device to device data bus
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* ownership change
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*/
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ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
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ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
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DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
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(CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
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DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
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@@ -440,7 +477,7 @@ int sdram_mmr_init_full(unsigned int unused)
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DDR_SCH_DEVTODEV);
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/* assigning the SDRAM size */
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unsigned long long size = sdram_calculate_size();
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unsigned long long size = sdram_calculate_size(plat);
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/* If the size is invalid, use default Config size */
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if (size <= 0)
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hw_size = PHYS_SDRAM_1_SIZE;
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@@ -462,18 +499,17 @@ int sdram_mmr_init_full(unsigned int unused)
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/* Enable or disable the SDRAM ECC */
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if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
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setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
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setbits_le32(plat->hmc + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
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clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
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clrbits_le32(plat->hmc + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
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setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
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setbits_le32(plat->hmc + ECCCTRL2,
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(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
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DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
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writel(DDR_HMC_ERRINTEN_INTMASK,
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SOCFPGA_SDR_ADDRESS + ERRINTENS);
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hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
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/* Enable non-secure writes to HMC Adapter for SDRAM ECC */
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writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
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@@ -482,39 +518,98 @@ int sdram_mmr_init_full(unsigned int unused)
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if (!cpu_has_been_warmreset())
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sdram_init_ecc_bits(&bd);
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} else {
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clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
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clrbits_le32(plat->hmc + ECCCTRL1,
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(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
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DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
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clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
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clrbits_le32(plat->hmc + ECCCTRL2,
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(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
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DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
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}
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sdram_size_check(&bd);
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priv->info.base = bd.bi_dram[0].start;
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priv->info.size = gd->ram_size;
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debug("DDR: HMC init success\n");
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return 0;
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}
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/**
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* sdram_calculate_size() - Calculate SDRAM size
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*
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* Calculate SDRAM device size based on SDRAM controller parameters.
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* Size is specified in bytes.
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*/
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phys_size_t sdram_calculate_size(void)
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static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
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{
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u32 dramaddrw = hmc_readl(DRAMADDRW);
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struct altera_sdram_platdata *plat = dev->platdata;
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fdt_addr_t addr;
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|
||||
phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
|
||||
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
|
||||
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
|
||||
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
|
||||
DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
|
||||
addr = dev_read_addr_index(dev, 0);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
plat->ddr_sch = (void __iomem *)addr;
|
||||
|
||||
size *= (2 << (hmc_ecc_readl(DDRIOCTRL) &
|
||||
DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
|
||||
addr = dev_read_addr_index(dev, 1);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
plat->iomhc = (void __iomem *)addr;
|
||||
|
||||
return size;
|
||||
addr = dev_read_addr_index(dev, 2);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
plat->hmc = (void __iomem *)addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int altera_sdram_probe(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
struct altera_sdram_priv *priv = dev_get_priv(dev);
|
||||
|
||||
ret = reset_get_bulk(dev, &priv->resets);
|
||||
if (ret) {
|
||||
dev_err(dev, "Can't get reset: %d\n", ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
reset_deassert_bulk(&priv->resets);
|
||||
|
||||
if (sdram_mmr_init_full(dev) != 0) {
|
||||
puts("SDRAM init failed.\n");
|
||||
goto failed;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
failed:
|
||||
reset_release_bulk(&priv->resets);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int altera_sdram_get_info(struct udevice *dev,
|
||||
struct ram_info *info)
|
||||
{
|
||||
struct altera_sdram_priv *priv = dev_get_priv(dev);
|
||||
|
||||
info->base = priv->info.base;
|
||||
info->size = priv->info.size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct ram_ops altera_sdram_ops = {
|
||||
.get_info = altera_sdram_get_info,
|
||||
};
|
||||
|
||||
static const struct udevice_id altera_sdram_ids[] = {
|
||||
{ .compatible = "altr,sdr-ctl-s10" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(altera_sdram) = {
|
||||
.name = "altr_sdr_ctl",
|
||||
.id = UCLASS_RAM,
|
||||
.of_match = altera_sdram_ids,
|
||||
.ops = &altera_sdram_ops,
|
||||
.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
|
||||
.probe = altera_sdram_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
|
||||
};
|
||||
|
||||
188
drivers/ddr/altera/sdram_s10.h
Normal file
188
drivers/ddr/altera/sdram_s10.h
Normal file
@@ -0,0 +1,188 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SDRAM_S10_H_
|
||||
#define _SDRAM_S10_H_
|
||||
|
||||
#define DDR_TWR 15
|
||||
#define DDR_READ_LATENCY_DELAY 40
|
||||
#define DDR_ACTIVATE_FAWBANK 0x1
|
||||
|
||||
/* ECC HMC registers */
|
||||
#define DDRIOCTRL 0x8
|
||||
#define DDRCALSTAT 0xc
|
||||
#define DRAMADDRWIDTH 0xe0
|
||||
#define ECCCTRL1 0x100
|
||||
#define ECCCTRL2 0x104
|
||||
#define ERRINTEN 0x110
|
||||
#define ERRINTENS 0x114
|
||||
#define INTMODE 0x11c
|
||||
#define INTSTAT 0x120
|
||||
#define AUTOWB_CORRADDR 0x138
|
||||
#define ECC_REG2WRECCDATABUS 0x144
|
||||
#define ECC_DIAGON 0x150
|
||||
#define ECC_DECSTAT 0x154
|
||||
#define HPSINTFCSEL 0x210
|
||||
#define RSTHANDSHAKECTRL 0x214
|
||||
#define RSTHANDSHAKESTAT 0x218
|
||||
|
||||
#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003
|
||||
#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0)
|
||||
#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
|
||||
#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8)
|
||||
#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0)
|
||||
#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8)
|
||||
#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0)
|
||||
#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16)
|
||||
#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0)
|
||||
#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0)
|
||||
#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1)
|
||||
#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0)
|
||||
#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1)
|
||||
#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16)
|
||||
#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0)
|
||||
#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff
|
||||
#define DDR_HMC_CORE2SEQ_INT_REQ 0xF
|
||||
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
|
||||
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
|
||||
|
||||
#define DDR_HMC_ERRINTEN_INTMASK \
|
||||
(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
|
||||
DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
|
||||
|
||||
/* NOC DDR scheduler */
|
||||
#define DDR_SCH_ID_COREID 0
|
||||
#define DDR_SCH_ID_REVID 0x4
|
||||
#define DDR_SCH_DDRCONF 0x8
|
||||
#define DDR_SCH_DDRTIMING 0xc
|
||||
#define DDR_SCH_DDRMODE 0x10
|
||||
#define DDR_SCH_READ_LATENCY 0x14
|
||||
#define DDR_SCH_ACTIVATE 0x38
|
||||
#define DDR_SCH_DEVTODEV 0x3c
|
||||
#define DDR_SCH_DDR4TIMING 0x40
|
||||
|
||||
#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0
|
||||
#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6
|
||||
#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12
|
||||
#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18
|
||||
#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21
|
||||
#define DDR_SCH_DDRTIMING_WRTORD_OFF 26
|
||||
#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31
|
||||
#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1
|
||||
#define DDR_SCH_ACTIVATE_RRD_OFF 0
|
||||
#define DDR_SCH_ACTIVATE_FAW_OFF 4
|
||||
#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10
|
||||
#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0
|
||||
#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2
|
||||
#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
|
||||
|
||||
/* HMC MMR IO48 registers */
|
||||
#define CTRLCFG0 0x28
|
||||
#define CTRLCFG1 0x2c
|
||||
#define DRAMTIMING0 0x50
|
||||
#define CALTIMING0 0x7c
|
||||
#define CALTIMING1 0x80
|
||||
#define CALTIMING2 0x84
|
||||
#define CALTIMING3 0x88
|
||||
#define CALTIMING4 0x8c
|
||||
#define CALTIMING9 0xa0
|
||||
#define DRAMADDRW 0xa8
|
||||
#define DRAMSTS 0xec
|
||||
#define NIOSRESERVED0 0x110
|
||||
#define NIOSRESERVED1 0x114
|
||||
#define NIOSRESERVED2 0x118
|
||||
|
||||
#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
|
||||
(((x) >> 0) & 0x1F)
|
||||
#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
|
||||
(((x) >> 5) & 0x1F)
|
||||
#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
|
||||
(((x) >> 10) & 0xF)
|
||||
#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
|
||||
(((x) >> 14) & 0x3)
|
||||
#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
|
||||
(((x) >> 16) & 0x7)
|
||||
|
||||
#define CTRLCFG0_CFG_MEMTYPE(x) \
|
||||
(((x) >> 0) & 0xF)
|
||||
#define CTRLCFG0_CFG_DIMM_TYPE(x) \
|
||||
(((x) >> 4) & 0x7)
|
||||
#define CTRLCFG0_CFG_AC_POS(x) \
|
||||
(((x) >> 7) & 0x3)
|
||||
#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
|
||||
(((x) >> 9) & 0x1F)
|
||||
|
||||
#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
|
||||
(((x) >> 0) & 0x1F)
|
||||
#define CTRLCFG1_CFG_ADDR_ORDER(x) \
|
||||
(((x) >> 5) & 0x3)
|
||||
#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
|
||||
(((x) >> 7) & 0x1)
|
||||
|
||||
#define DRAMTIMING0_CFG_TCL(x) \
|
||||
(((x) >> 0) & 0x7F)
|
||||
|
||||
#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_PCH(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_ACT(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
|
||||
#define CALTIMING1_CFG_RD_TO_RD(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_WR(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING2_CFG_WR_TO_WR(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
|
||||
(((x) >> 18) & 0x3F)
|
||||
#define CALTIMING3_CFG_WR_TO_PCH(x) \
|
||||
(((x) >> 24) & 0x3F)
|
||||
|
||||
#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
|
||||
(((x) >> 0) & 0x3F)
|
||||
#define CALTIMING4_CFG_PCH_TO_VALID(x) \
|
||||
(((x) >> 6) & 0x3F)
|
||||
#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
|
||||
(((x) >> 12) & 0x3F)
|
||||
#define CALTIMING4_CFG_ARF_TO_VALID(x) \
|
||||
(((x) >> 18) & 0xFF)
|
||||
#define CALTIMING4_CFG_PDN_TO_VALID(x) \
|
||||
(((x) >> 26) & 0x3F)
|
||||
|
||||
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
|
||||
(((x) >> 0) & 0xFF)
|
||||
|
||||
/* Firewall DDR scheduler MPFE */
|
||||
#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
|
||||
#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
|
||||
|
||||
#endif /* _SDRAM_S10_H_ */
|
||||
Reference in New Issue
Block a user