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mirror of https://xff.cz/git/u-boot/ synced 2025-11-01 19:05:51 +01:00

ARM: dts: stm32mp15: alignment with v5.19

Device tree alignment with Linux kernel v5.19-rc1

- ARM: dts: stm32: Add alternate pinmux for ethernet0 pins
- ARM: dts: stm32: Add alternate pinmux for mco2 pins
- ARM: dts: stm32: fix pinctrl node name warnings (MPU soc)
- ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group
- dt-bindings: clock: add IDs for SCMI clocks on stm32mp15
- dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
- dt-bindings: clock: stm32mp15: rename CK_SCMI define
- dt-bindings: reset: stm32mp15: rename RST_SCMI define
- dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains
  on stm32mp15
- dt-bindings: clk: cleanup comments
- ARM: dts: align SPI NOR node name with dtschema
- ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15
- ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)
- ARM: dts: stm32: move SCMI related nodes in a dedicated file for
  stm32mp15

+ patch from stm32-dt-for-v5.19-fixes-2

- ARM: dts: stm32: move SCMI related nodes in a dedicated file for
  stm32mp15
- ARM: dts: stm32: fix pwr regulators references to use scmi
- ARM: dts: stm32: use the correct clock source for CEC on stm32mp151
- ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board
- ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI
- ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay
2022-07-05 16:55:54 +02:00
parent cb8edb996b
commit 69ef98b209
12 changed files with 558 additions and 9 deletions

View File

@@ -7,10 +7,10 @@
*/
/*
* List of clocks wich are not derived from system clock (SYSCLOCK)
* List of clocks which are not derived from system clock (SYSCLOCK)
*
* The index of these clocks is the secondary index of DT bindings
* (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
* (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
*
* e.g:
<assigned-clocks = <&rcc 1 CLK_LSE>;

View File

@@ -248,4 +248,27 @@
#define STM32MP1_LAST_CLK 232
/* SCMI clock identifiers */
#define CK_SCMI_HSE 0
#define CK_SCMI_HSI 1
#define CK_SCMI_CSI 2
#define CK_SCMI_LSE 3
#define CK_SCMI_LSI 4
#define CK_SCMI_PLL2_Q 5
#define CK_SCMI_PLL2_R 6
#define CK_SCMI_MPU 7
#define CK_SCMI_AXI 8
#define CK_SCMI_BSEC 9
#define CK_SCMI_CRYP1 10
#define CK_SCMI_GPIOZ 11
#define CK_SCMI_HASH1 12
#define CK_SCMI_I2C4 13
#define CK_SCMI_I2C6 14
#define CK_SCMI_IWDG1 15
#define CK_SCMI_RNG1 16
#define CK_SCMI_RTC 17
#define CK_SCMI_RTCAPB 18
#define CK_SCMI_SPI6 19
#define CK_SCMI_USART1 20
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */

View File

@@ -39,3 +39,4 @@
#define STM32MP_PKG_AD 0x8
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */

View File

@@ -106,4 +106,18 @@
#define GPIOJ_R 19785
#define GPIOK_R 19786
/* SCMI reset domain identifiers */
#define RST_SCMI_SPI6 0
#define RST_SCMI_I2C4 1
#define RST_SCMI_I2C6 2
#define RST_SCMI_USART1 3
#define RST_SCMI_STGEN 4
#define RST_SCMI_GPIOZ 5
#define RST_SCMI_CRYP1 6
#define RST_SCMI_HASH1 7
#define RST_SCMI_RNG1 8
#define RST_SCMI_MDMA 9
#define RST_SCMI_MCU 10
#define RST_SCMI_MCU_HOLD_BOOT 11
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */