* Patches by Udi Finkelstein, 2 June 2003:

- Added support for custom keyboards, initialized by defining a
    board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
  - Added support for the RBC823 board.
  - cpu/mpc8xx/lcd.c now automatically calculates the
    Horizontal Pixel Count field.

* Fix alignment problem in BOOTP (dhcp_leasetime option)
  [pointed out by Nicolas Lacressonni�re, 2 Jun 2003]

* Patch by Mark Rakes, 14 May 2003:
  add support for Intel e1000 gig cards.

* Patch by Nye Liu, 3 Jun 2003:
  fix critical typo in MAMR definition (include/mpc8xx.h)

* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.

* Patch by Klaus Heydeck, 2 Jun 2003
  Minor changes for KUP4K configuration

CHANGELOG

@@ -2,6 +2,27 @@
 Changes since U-Boot 0.3.1:
 ======================================================================
 
+* Patches by Udi Finkelstein, 2 June 2003:
+  - Added support for custom keyboards, initialized by defining a
+    board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
+  - Added support for the RBC823 board.
+  - cpu/mpc8xx/lcd.c now automatically calculates the
+    Horizontal Pixel Count field.
+
+* Fix alignment problem in BOOTP (dhcp_leasetime option)
+  [pointed out by Nicolas Lacressonni<6E>re, 2 Jun 2003]
+
+* Patch by Mark Rakes, 14 May 2003:
+  add support for Intel e1000 gig cards.
+
+* Patch by Nye Liu, 3 Jun 2003:
+  fix critical typo in MAMR definition (include/mpc8xx.h)
+
+* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
+
+* Patch by Klaus Heydeck, 2 Jun 2003
+  Minor changes for KUP4K configuration
+
 * Patch by Marc Singer, 29 May 2003:
   Fixed rarp boot method for IA32 and other little-endian CPUs.
 

MAKEALL

@@ -32,11 +32,11 @@ LIST_8xx="	\
 	IVMS8		IVMS8_128	IVMS8_256	KUP4K           \
 	LANTEC	        lwmon   	MBX		MBX860T		\
 	MHPC		MVS1		NETVIA		NX823		\
-	pcu_e		R360MPI		RPXClassic	RPXlite		\
+	pcu_e		R360MPI		RBC823		RPXClassic	\
-	RRvision	SM850		SPD823TS	svm_sc8xx	\
+	RPXlite		RRvision	SM850		SPD823TS	\
-	SXNI855T	TOP860		TQM823L		TQM823L_LCD	\
+	svm_sc8xx	SXNI855T	TOP860		TQM823L		\
-	TQM850L		TQM855L		TQM860L		TTTech		\
+	TQM823L_LCD	TQM850L		TQM855L		TQM860L		\
-	v37								\
+	TTTech		v37						\
 "
 
 #########################################################################

Makefile

@@ -314,6 +314,9 @@ pcu_e_config:		unconfig
 R360MPI_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx r360mpi
 
+RBC823_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx rbc823
+
 RPXClassic_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx RPXClassic
 

README

@@ -344,7 +344,7 @@ The following options need to be configured:
 		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
 		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
 		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA
+		CONFIG_NETVIA,     CONFIG_RBC823
 
 		ARM based boards:
 		-----------------
@@ -688,6 +688,9 @@ The following options need to be configured:
 		CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
 
 - NETWORK Support (PCI):
+		CONFIG_E1000
+		Support for Intel 8254x gigabit chips.
+		
 		CONFIG_EEPRO100
 		Support for Intel 82557/82559/82559ER chips.
 		Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
@@ -766,6 +769,13 @@ The following options need to be configured:
 		and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
 		or CONFIG_VIDEO_SED13806_16BPP
 
+- Keyboard Support:
+                CONFIG_KEYBOARD
+
+                Define this to enable a custom keyboard support.
+                This simply calls drv_keyboard_init() which must be
+                defined in your board-specific files.
+                The only board using this so far is RBC823.
 
 - LCD Support:	CONFIG_LCD
 

board/kup4k/flash.c

@@ -172,6 +172,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	value = value|(value<<16);
 
 	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
 	case FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
@@ -191,6 +194,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);			/* => no or unknown flash */

board/kup4k/kup4k.c

@@ -54,10 +54,7 @@ const uint sdram_table[] =
 	/*
 	 * Single Read. (Offset 0 in UPMA RAM)
 	 */
-	0x1F07FC04,
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
-	0xEEAEFC04,
-	0x11ADFC04,
-	0xEFBBBC00,
 	0x1FF77C47, /* last */
 
 	/*
@@ -68,43 +65,27 @@ const uint sdram_table[] =
 	 * sequence, which is executed by a RUN command.
 	 *
 	 */
-	0x1FF77C35,
+		    0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
-	0xEFEABC34,
-	0x1FB57C35,  /* last */
 
 	/*
 	 * Burst Read. (Offset 8 in UPMA RAM)
 	 */
-	0x1F07FC04,
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
-	0xEEAEFC04,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
-	0x10ADFC04,
-	0xF0AFFC00,
-	0xF0AFFC00,
-	0xF1AFFC00,
-	0xEFBBBC00,
-	0x1FF77C47, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Single Write. (Offset 18 in UPMA RAM)
 	 */
-	0x1F27FC04,
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
-	0xEEAEBC00,
-	0x01B93C04,
-    0x1FF77C47, /* last */
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
 	/*
 	 * Burst Write. (Offset 20 in UPMA RAM)
 	 */
-	0x1F07FC04,
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
-	0xEEAEBC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
-	0x10AD7C00,
-	0xF0AFFC00,
-	0xF0AFFC00,
-	0xE1BBBC04,
-	0x1FF77C47, /* last */
 					    _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
@@ -112,12 +93,8 @@ const uint sdram_table[] =
 	/*
 	 * Refresh  (Offset 30 in UPMA RAM)
 	 */
-	0x1FF5FC84,
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
-	0xFFFFFC04,
-	0xFFFFFC04,
-	0xFFFFFC84,
-	0xFFFFFC07, /* last */
 				_NOT_USED_, _NOT_USED_,
 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 
@@ -146,13 +123,14 @@ int checkboard (void)
 
 long int initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0 = 0;
 	long int size_b1 = 0;
 	long int size_b2 = 0;
 
-    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+	upmconfig (UPMA, (uint *) sdram_table,
+			 sizeof (sdram_table) / sizeof (uint));
 
 	/*
 	 * Preliminary prescaler for refresh (depends on number of
@@ -178,55 +156,61 @@ long int initdram (int board_type)
 
 	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
 
-    udelay(200);
+	udelay (200);
 
 	/* perform SDRAM initializsation sequence */
 
 	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
-    udelay(1);
+	udelay (1);
 	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
-    udelay(1);
+	udelay (1);
 	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
-    udelay(1);
+	udelay (1);
 
 	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
-	udelay(1);
+	udelay (1);
 	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
-	udelay(1);
+	udelay (1);
 	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
-    udelay(1);
+	udelay (1);
 
 	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
-	udelay(1);
+	udelay (1);
 	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
-	udelay(1);
+	udelay (1);
 	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
-    udelay(1);
+	udelay (1);
-
 
 	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
 	udelay (1000);
 
+#if 0							/* 3 x 8MB */
 	size_b0 = 0x00800000;
 	size_b1 = 0x00800000;
 	size_b2 = 0x00800000;
-
-
 	memctl->memc_mptpr = CFG_MPTPR;
-	udelay(1000);
+	udelay (1000);
-
 	memctl->memc_or1 = 0xFF800A00;
 	memctl->memc_br1 = 0x00000081;
-
 	memctl->memc_or2 = 0xFF000A00;
 	memctl->memc_br2 = 0x00800081;
-
 	memctl->memc_or3 = 0xFE000A00;
 	memctl->memc_br3 = 0x01000081;
+#else							/* 3 x 16 MB */
+	size_b0 = 0x01000000;
+	size_b1 = 0x01000000;
+	size_b2 = 0x01000000;
+	memctl->memc_mptpr = CFG_MPTPR;
+	udelay (1000);
+	memctl->memc_or1 = 0xFF000A00;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_or2 = 0xFE000A00;
+	memctl->memc_br2 = 0x01000081;
+	memctl->memc_or3 = 0xFC000A00;
+	memctl->memc_br3 = 0x02000081;
+#endif
 
-    udelay(10000);
+	udelay (10000);
-
 
 	return (size_b0 + size_b1 + size_b2);
 }
@@ -241,9 +225,10 @@ long int initdram (int board_type)
  * - short between data lines
  */
 #if 0
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile long int *addr;
 	ulong cnt, val;
@@ -252,7 +237,7 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
 
 	memctl->memc_mamr = mamr_value;
 
-    for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
 		addr = base + cnt;		/* pointer arith! */
 
 		save[i++] = *addr;
@@ -270,14 +255,14 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
 		return (0);
 	}
 
-    for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
 		addr = base + cnt;		/* pointer arith! */
 
 		val = *addr;
 		*addr = save[--i];
 
 		if (val != (~cnt)) {
-	    return (cnt * sizeof(long));
+			return (cnt * sizeof (long));
 		}
 	}
 	return (maxsize);
@@ -289,13 +274,13 @@ int misc_init_r (void)
 	DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_STATUS_LED
-	volatile immap_t	*immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 #endif
 #ifdef CONFIG_KUP4K_LOGO
 	bd_t *bd = gd->bd;
 
 
-	lcd_logo(bd);
+	lcd_logo (bd);
 #endif							/* CONFIG_KUP4K_LOGO */
 #ifdef CONFIG_IDE_LED
 	/* Configure PA8 as output port */
@@ -304,27 +289,43 @@ int misc_init_r (void)
 	immap->im_ioport.iop_papar &= ~0x80;
 	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
 #endif
-	return(0);
+	return (0);
 }
 
 #ifdef CONFIG_KUP4K_LOGO
-void lcd_logo(bd_t *bd){
+
+
+#define PB_LCD_PWM	((uint)0x00004000)	/* PB 17 */
+
+void lcd_logo (bd_t * bd)
+{
+
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+
 
 	FB_INFO_S1D13xxx fb_info;
 	S1D_INDEX s1dReg;
 	S1D_VALUE s1dValue;
-    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl;
 	ushort i;
 	uchar *fb;
 	int rs, gs, bs;
 	int r = 8, g = 8, b = 4;
-    int r1,g1,b1;
+	int r1, g1, b1;
+
+	immr->im_cpm.cp_pbpar &= ~PB_LCD_PWM;
+	immr->im_cpm.cp_pbodr &= ~PB_LCD_PWM;
+	immr->im_cpm.cp_pbdat &= ~PB_LCD_PWM;	/* set to 0 = enabled */
+	immr->im_cpm.cp_pbdir |= PB_LCD_PWM;
+
 
 /*----------------------------------------------------------------------------- */
-/**/
+	 /**/
 /* Initialize the chip and the frame buffer driver. */
-/**/
+			 /**/
 /*----------------------------------------------------------------------------- */
 			memctl = &immr->im_memctl;
 /*    memctl->memc_or5 = 0xFFC007F0;    / * 4 MB  17 WS or externel TA */
@@ -337,78 +338,80 @@ void lcd_logo(bd_t *bd){
 
 
 
-    fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
+	fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
-    fb_info.RegAddr =  (unsigned char*)(S1D_PHYSICAL_REG_ADDR);
+	fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
 
-    if ((((S1D_VALUE*)fb_info.RegAddr)[0] != 0x28) || (((S1D_VALUE*)fb_info.RegAddr)[1] != 0x14))
+	if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
-    {
+		|| (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
-	  printf("Warning:LCD Controller S1D13706 not found\n");
+		printf ("Warning:LCD Controller S1D13706 not found\n");
 		return;
 	}
 
 	/* init controller */
-    for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
+	for (i = 0; i < sizeof (aS1DRegs) / sizeof (aS1DRegs[0]); i++) {
-    {
 		s1dReg = aS1DRegs[i].Index;
 		s1dValue = aS1DRegs[i].Value;
 /*      printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
-        ((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
+		((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
+				s1dValue;
 	}
 
 #undef MONOCHROME
 #ifdef MONOCHROME
-   	switch(bd->bi_busfreq){
+	switch (bd->bi_busfreq) {
 #if 0
 	case 24000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x28;
 		break;
 	case 32000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x33;
 		break;
 #endif
 	case 40000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x40;
 		break;
 	case 48000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x4C;
 		break;
 	default:
-			printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
+		printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
+				bd->bi_busfreq);
 	case 64000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x69;
 		break;
 	}
-	((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
+	((S1D_VALUE *) fb_info.RegAddr)[0x10] = 0x00;
 #else
-	   	switch(bd->bi_busfreq){
+	switch (bd->bi_busfreq) {
 #if 0
 	case 24000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
 		break;
 	case 32000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
 		break;
 #endif
 	case 40000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
 		break;
 	case 48000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
 		break;
 	default:
-			printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
+		printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
+				bd->bi_busfreq);
 	case 64000000:
-			((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
+		((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
-			((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
+		((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
 		break;
 	}
 #endif
@@ -418,24 +421,26 @@ void lcd_logo(bd_t *bd){
 	rs = 256 / (r - 1);
 	gs = 256 / (g - 1);
 	bs = 256 / (b - 1);
-	for(i=0;i<256;i++){
+	for (i = 0; i < 256; i++) {
-       r1=(rs * ((i / (g * b)) % r)) * 255;
+		r1 = (rs * ((i / (g * b)) % r)) * 255;
-       g1=(gs * ((i / b) % g)) * 255;
+		g1 = (gs * ((i / b) % g)) * 255;
-       b1=(bs * ((i) % b)) * 255;
+		b1 = (bs * ((i) % b)) * 255;
 /*     printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
-       S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
+		S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
+						   (b1 >> 4));
 	}
 
 	/* copy bitmap */
 	fb = (char *) (fb_info.VmemAddr);
-	memcpy (fb, (uchar *)CONFIG_KUP4K_LOGO, 320 * 240);
+	memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
 }
 #endif							/* CONFIG_KUP4K_LOGO */
 
 #ifdef CONFIG_IDE_LED
 void ide_led (uchar led, uchar status)
 {
-	volatile immap_t	*immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
 	/* We have one led for both pcmcia slots */
 	if (status) {				/* led on */
 		immap->im_ioport.iop_padat &= ~0x80;

board/kup4k/s1d13706.h

@@ -50,8 +50,6 @@ typedef struct
 
 static S1D_REGS aS1DRegs[] =
 {
-
-
 	{0x04,0x10},	/* BUSCLK MEMCLK Config Register */
 #if 0
 	{0x05,0x32},	/* PCLK Config  Register  */
@@ -106,10 +104,10 @@ static S1D_REGS aS1DRegs[] =
 	{0xA9,0x80},	/* GPIO Config Register 1 */
 	{0xAC,0x01},	/* GPIO Status Control Register 0 */
 	{0xAD,0x00},	/* GPIO Status Control Register 1 */
-    {0xB0,0x00},   /* PWM CV Clock Control Register */
+	{0xB0,0x10},	/* PWM CV Clock Control Register */
-    {0xB1,0x00},   /* PWM CV Clock Config Register */
+	{0xB1,0x80},	/* PWM CV Clock Config Register */
 	{0xB2,0x00},	/* CV Clock Burst Length Register */
-    {0xB3,0x00},   /* PWM Clock Duty Cycle Register */
+	{0xB3,0xA0},	/* PWM Clock Duty Cycle Register */
 	{0xAD,0x80},	/* reset seq */
 	{0x70,0x03},	/*  */
 };

board/rbc823/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o kbd.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $^
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/rbc823/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RBC823 boards
+#
+
+TEXT_BASE = 0xFFF00000

board/rbc823/flash.c

@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	/* Detect size */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	/* Setup offsets */
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	size_b1 = 0 ;
+
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].sector_count = -1;
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ * Fix this to support variable sector sizes
+*/
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case FLASH_MAN_AMD:	printf ("AMD ");		break;
+		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+		case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK)
+	{
+		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+			break;
+		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+					break;
+		default:		printf ("Unknown Chip Type\n");
+					break;
+	}
+
+	if (info->size >> 20) {
+	    printf ("  Size: %ld MB in %d Sectors\n",
+	    	info->size >> 20,
+		info->sector_count);
+	} else {
+	    printf ("  Size: %ld KB in %d Sectors\n",
+	    	info->size >> 10,
+		info->sector_count);
+	}
+
+	puts ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i)
+	{
+		if ((i % 5) == 0)
+		{
+			puts ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	putc ('\n');
+	return;
+}
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	volatile unsigned char *caddr;
+	char value;
+
+	caddr = (volatile unsigned char *)addr ;
+
+	/* Write auto select command: read Manufacturer ID */
+
+#if 0
+	printf("Base address is: %08x\n", caddr);
+#endif
+
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	value = caddr[0];
+
+#if 0
+	printf("Manufact ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case 0x01:
+		case AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+		break;
+
+		case FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	value = caddr[1];			/* device ID		*/
+#if 0
+	printf("Device ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case AMD_ID_LV040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;				/* => 512Kb 		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++)
+	{
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN)
+	{
+		caddr = (volatile unsigned char *)info->start[0];
+		*caddr = 0xF0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile unsigned char *)(info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile unsigned char *)(info->start[l_sect]);
+
+	while ((addr[0] & 0xFF) != 0xFF)
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *)info->start[0];
+
+	addr[0] = 0xF0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
+				*cdest,*cdata;
+	ulong start;
+	int flag, count = 4 ;
+
+	cdest = (volatile unsigned char *)dest ;
+	cdata = (volatile unsigned char *)&data ;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	while(count--)
+	{
+	    /* Disable interrupts which might cause a timeout here */
+	    flag = disable_interrupts();
+
+	    addr[0x0555] = 0xAA;
+	    addr[0x02AA] = 0x55;
+	    addr[0x0555] = 0xA0;
+
+	    *cdest = *cdata;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	    	enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((*cdest ^ *cdata) & 0x80)
+	    {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	    }
+
+	    cdata++ ;
+	    cdest++ ;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */

board/rbc823/kbd.c

@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Modified by Udi Finkelstein
+ *
+ * This file includes communication routines for SMC1 that can run even if
+ * SMC2 have already been initialized.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <commproc.h>
+#include <devices.h>
+#include <lcd.h>
+
+#define	SMC_INDEX	0
+#define PROFF_SMC	PROFF_SMC1
+#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
+
+#define RBC823_KBD_BAUDRATE	38400
+#define CPM_KEYBOARD_BASE	0x1000
+/*
+ * Minimal serial functions needed to use one of the SMC ports
+ * as serial console interface.
+ */
+
+void smc1_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+
+	/* Set up the baud rate generator.
+	 * See 8xx_io/commproc.c for details.
+	 *
+	 * Wire BRG2 to SMC1, BRG1 to SMC2
+	 */
+
+	cp->cp_simode = 0x00001000;
+
+	cp->cp_brgc2 =
+		(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
+}
+
+int smc1_init (void)
+{
+        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile smc_t *sp;
+	volatile smc_uart_t *up;
+	volatile cbd_t *tbdf, *rbdf;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+	uint	dpaddr;
+
+	/* initialize pointers to SMC */
+
+	sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
+	up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
+
+	/* Disable transmitter/receiver.
+	*/
+	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+
+	/* Enable SDMA.
+	*/
+	im->im_siu_conf.sc_sdcr = 1;
+
+	/* clear error conditions */
+#ifdef	CFG_SDSR
+	im->im_sdma.sdma_sdsr = CFG_SDSR;
+#else
+	im->im_sdma.sdma_sdsr = 0x83;
+#endif
+
+	/* clear SDMA interrupt mask */
+#ifdef	CFG_SDMR
+	im->im_sdma.sdma_sdmr = CFG_SDMR;
+#else
+	im->im_sdma.sdma_sdmr = 0x00;
+#endif
+
+	/* Use Port B for SMC1 instead of other functions.
+	*/
+	cp->cp_pbpar |=  0x000000c0;
+	cp->cp_pbdir &= ~0x000000c0;
+	cp->cp_pbodr &= ~0x000000c0;
+
+	/* Set the physical address of the host memory buffers in
+	 * the buffer descriptors.
+	 */
+
+#ifdef CFG_ALLOC_DPRAM
+	dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
+#else
+	dpaddr = CPM_KEYBOARD_BASE ;
+#endif
+
+	/* Allocate space for two buffer descriptors in the DP ram.
+	 * For now, this address seems OK, but it may have to
+	 * change with newer versions of the firmware.
+	 * damm: allocating space after the two buffers for rx/tx data
+	 */
+
+	rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
+	rbdf->cbd_bufaddr = (uint) (rbdf+2);
+	rbdf->cbd_sc = 0;
+	tbdf = rbdf + 1;
+	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+	tbdf->cbd_sc = 0;
+
+	/* Set up the uart parameters in the parameter ram.
+	*/
+	up->smc_rbase = dpaddr;
+	up->smc_tbase = dpaddr+sizeof(cbd_t);
+	up->smc_rfcr = SMC_EB;
+	up->smc_tfcr = SMC_EB;
+
+	/* Set UART mode, 8 bit, no parity, one stop.
+	 * Enable receive and transmit.
+	 */
+	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
+
+	/* Mask all interrupts and remove anything pending.
+	*/
+	sp->smc_smcm = 0;
+	sp->smc_smce = 0xff;
+
+	/* Set up the baud rate generator.
+	*/
+	smc1_setbrg ();
+
+	/* Make the first buffer the only buffer.
+	*/
+	tbdf->cbd_sc |= BD_SC_WRAP;
+	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+
+	/* Single character receive.
+	*/
+	up->smc_mrblr = 1;
+	up->smc_maxidl = 0;
+
+	/* Initialize Tx/Rx parameters.
+	*/
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	/* Enable transmitter/receiver.
+	*/
+	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+
+	return (0);
+}
+
+void smc1_putc(const char c)
+{
+	volatile cbd_t		*tbdf;
+	volatile char		*buf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
+
+	/* Wait for last character to go.
+	*/
+
+	buf = (char *)tbdf->cbd_bufaddr;
+
+	*buf = c;
+	tbdf->cbd_datlen = 1;
+	tbdf->cbd_sc |= BD_SC_READY;
+	__asm__("eieio");
+
+	while (tbdf->cbd_sc & BD_SC_READY) {
+		WATCHDOG_RESET ();
+		__asm__("eieio");
+	}
+}
+
+int smc1_getc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile unsigned char	*buf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+	unsigned char		c;
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+
+	/* Wait for character to show up.
+	*/
+	buf = (unsigned char *)rbdf->cbd_bufaddr;
+
+	while (rbdf->cbd_sc & BD_SC_EMPTY)
+		WATCHDOG_RESET ();
+
+	c = *buf;
+	rbdf->cbd_sc |= BD_SC_EMPTY;
+
+	return(c);
+}
+
+int smc1_tstc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+
+	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
+}
+
+/* search for keyboard and register it if found */
+int drv_keyboard_init(void)
+{
+	int error = 0;
+	device_t kbd_dev;
+
+	if (0) {
+		/* register the keyboard */
+		memset (&kbd_dev, 0, sizeof(device_t));
+		strcpy(kbd_dev.name, "kbd");
+		kbd_dev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+		kbd_dev.putc = NULL;
+		kbd_dev.puts = NULL;
+		kbd_dev.getc = smc1_getc;
+		kbd_dev.tstc = smc1_tstc;
+		error = device_register (&kbd_dev);
+	} else {
+		lcd_is_enabled = 0;
+		lcd_disable();
+	}
+	return error;
+}

board/rbc823/rbc823.c

@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+#include <linux/mtd/doc2000.h>
+
+extern int kbd_init(void);
+extern int drv_kbd_init(void);
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x1FF7FC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+const uint static_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
+	0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
+	0xFFFFFC04, 0xFFFFFC05, /* last */
+	                        _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
+	0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+    unsigned char *s = getenv("serial#");
+
+    if (!s || strncmp(s, "TQM8", 4)) {
+	printf ("### No HW ID - assuming RBC823\n");
+	return (0);
+    }
+
+    puts(s);
+    putc ('\n');
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    long int size_b0, size8, size9;
+
+    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+    /*
+     * 1 Bank of 64Mbit x 2 devices 
+     */
+    memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+    memctl->memc_mar  = 0x00000088;
+
+    /*
+     * Map controller SDRAM bank 0
+     */
+    memctl->memc_or4 = CFG_OR4_PRELIM;
+    memctl->memc_br4 = CFG_BR4_PRELIM;
+    memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+    udelay(200);
+
+    /* 
+     * Perform SDRAM initializsation sequence 
+     */
+    memctl->memc_mcr  = 0x80008105;	/* SDRAM bank 0 */
+    udelay(1);
+    memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
+    udelay(200);
+    memctl->memc_mcr  = 0x80008130;	/* SDRAM bank 0 - execute twice */
+    udelay(1);
+    memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
+    udelay(200); 
+
+    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+    udelay (1000);
+
+    /*
+     * Preliminary prescaler for refresh (depends on number of
+     * banks): This value is selected for four cycles every 62.4 us
+     * with two SDRAM banks or four cycles every 31.2 us with one
+     * bank. It will be adjusted after memory sizing.
+     */
+    memctl->memc_mptpr = CFG_MPTPR_2BK_4K; // 16: but should be: CFG_MPTPR_1BK_4K
+
+    /*
+     * Check Bank 0 Memory Size for re-configuration
+     *
+     * try 8 column mode
+     */
+    size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
+    udelay (1000);
+
+    /*
+     * try 9 column mode
+     */
+    size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
+
+    if (size8 < size9) {		/* leave configuration at 9 columns	*/
+	size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+    } else {				/* back to 8 columns			*/
+	size_b0 = size8;
+	memctl->memc_mamr = CFG_MAMR_8COL;
+	udelay(500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+    }
+
+    udelay (1000);
+
+    /*
+     * Adjust refresh rate depending on SDRAM type, both banks
+     * For types > 128 MBit leave it at the current (fast) rate
+     */
+    if ((size_b0 < 0x02000000) ) {
+	/* reduce to 15.6 us (62.4 us / quad) */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+	udelay(1000);
+    }
+
+    /* SDRAM Bank 0 is bigger - map first	*/
+
+    memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+    memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+    udelay(10000);
+
+    return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    volatile long int	 *addr;
+    long int		  cnt, val;
+
+    memctl->memc_mamr = mamr_value;
+
+    for (cnt = maxsize/sizeof(long)/2; cnt > 0; cnt >>= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	*addr = ~cnt;
+    }
+
+    /* write 0 to base address */
+    addr = base;
+    *addr = 0;
+
+    /* check at base address */
+    if ((val = *addr) != 0) {
+	return (0);
+    }
+
+    for (cnt = 1; cnt < maxsize/sizeof(long) ; cnt <<= 1) {
+	addr = base + cnt;	/* pointer arith! */
+
+	val = *addr;
+
+	if (val != (~cnt)) {
+	    return (cnt * sizeof(long));
+	}
+    }
+    return cnt * sizeof(long);
+    /* NOTREACHED */
+}
+
+void doc_init(void)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+    upmconfig(UPMB, (uint *)static_table, sizeof(static_table)/sizeof(uint));
+    memctl->memc_mbmr = MAMR_DSA_1_CYCL;
+
+    doc_probe(FLASH_BASE1_PRELIM);
+}
+

board/rbc823/u-boot.lds

@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+

common/devices.c

@@ -185,8 +185,8 @@ int devices_init (void)
 #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
 	drv_video_init ();
 #endif
-#ifdef CONFIG_WL_4PPM_KEYBOARD
+#ifdef CONFIG_KEYBOARD
-	drv_wlkbd_init ();
+	drv_keyboard_init ();
 #endif
 #ifdef CONFIG_LOGBUFFER
 	drv_logbuff_init ();

cpu/74xx_7xx/start.S

@@ -750,7 +750,7 @@ trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
-	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
+	li	r9, 0x100		/* reset vector always at 0x100 */
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */

cpu/mpc5xx/start.S

@@ -556,7 +556,7 @@ trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
-	rlwinm	r9, r7, 0, 22, 31	/* _start & 0x3FF	*/
+	li	r9, 0x100		/* reset vector always at 0x100 */
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */

cpu/mpc824x/start.S

@@ -695,7 +695,7 @@ trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
-	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
+	li	r9, 0x100		/* reset vector always at 0x100 */
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */

cpu/mpc8260/pci.c

@@ -170,7 +170,7 @@
 #endif
 
 #ifndef CFG_PCI_MSTR_MEMIO_SIZE 
-#define PCI_MSTR_MEMIO_SIZE 0x20000000          /* 512MB */ 
+#define PCI_MSTR_MEMIO_SIZE 0x10000000          /* 256 MB */ 
 #else 
 #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE 
 #endif

cpu/mpc8260/start.S

@@ -1028,7 +1028,7 @@ trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
-	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
+	li	r9, 0x100		/* reset vector always at 0x100 */
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */

cpu/mpc8xx/Makefile

@@ -31,7 +31,7 @@ START	= start.o kgdb.o
 OBJS	= bedbug_860.o commproc.o cpu.o cpu_init.o	\
 	  fec.o i2c.o interrupts.o lcd.o scc.o		\
 	  serial.o speed.o spi.o status_led.o\
-	  traps.o upatch.o video.o wlkbd.o
+	  traps.o upatch.o video.o
 
 all:	.depend $(START) $(LIB)
 

cpu/mpc8xx/lcd.c

@@ -36,7 +36,7 @@
 #if defined(CONFIG_POST)
 #include <post.h>
 #endif
-
+#include <lcd.h>
 
 #ifdef CONFIG_LCD
 
@@ -134,6 +134,19 @@ static vidinfo_t panel_info = {
 #endif /* CONFIG_KYOCERA_KCS057QV1AJ */
 /*----------------------------------------------------------------------*/
 
+/*----------------------------------------------------------------------*/
+#ifdef CONFIG_HITACHI_SP19X001_Z1A
+/*
+ *  Hitachi SP19X001-. Active, color, single scan.
+ */
+static vidinfo_t panel_info = {
+    640, 480, 154, 116, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH, CFG_HIGH,
+    LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
+		/* wbl, vpw, lcdac, wbf */
+};
+#endif /* CONFIG_HITACHI_SP19X001_Z1A */
+/*----------------------------------------------------------------------*/
+
 /*----------------------------------------------------------------------*/
 #ifdef CONFIG_NEC_NL6648AC33
 /*
@@ -307,7 +320,7 @@ static int lcd_line_length;
 static int lcd_color_fg;
 static int lcd_color_bg;
 
-static char lcd_is_enabled = 0;		/* Indicate that LCD is enabled	*/
+char lcd_is_enabled = 0;		/* Indicate that LCD is enabled	*/
 
 /*
  * Frame buffer memory information
@@ -395,7 +408,8 @@ static void	lcd_drawchars  (ushort x, ushort y, uchar *str, int count);
 static inline void lcd_puts_xy (ushort x, ushort y, uchar *s);
 static inline void lcd_putc_xy (ushort x, ushort y, uchar  c);
 
-static int	lcd_init (void *lcdbase);
+int	lcd_init (void *lcdbase);
+
 static void	lcd_ctrl_init (void *lcdbase);
 static void	lcd_enable (void);
 static void    *lcd_logo (void);
@@ -410,8 +424,11 @@ static int	lcd_getbgcolor (void);
 static void	lcd_setfgcolor (int color);
 static void	lcd_setbgcolor (int color);
 
+#if defined(CONFIG_RBC823)
+void	lcd_disable (void);
+#endif
+
 #ifdef	NOT_USED_SO_FAR
-static void	lcd_disable (void);
 static void	lcd_getcolreg (ushort regno,
 				ushort *red, ushort *green, ushort *blue);
 static int	lcd_getfgcolor (void);
@@ -675,7 +692,7 @@ int drv_lcd_init (void)
 
 /*----------------------------------------------------------------------*/
 
-static int lcd_init (void *lcdbase)
+int lcd_init (void *lcdbase)
 {
 	/* Initialize the lcd controller */
 	debug ("[LCD] Initializing LCD frambuffer at %p\n", lcdbase);
@@ -778,6 +795,7 @@ static void lcd_ctrl_init (void *lcdbase)
 	volatile lcd823_t *lcdp = &immr->im_lcd;
 
 	uint lccrtmp;
+	uint lchcr_hpc_tmp;
 
 	/* Initialize the LCD control register according to the LCD
 	 * parameters defined.  We do everything here but enable
@@ -808,6 +826,9 @@ static void lcd_ctrl_init (void *lcdbase)
 
 	/* Initialize LCD controller bus priorities.
 	 */
+#ifdef CONFIG_RBC823
+	immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1;	/* RAID = 01, LAID = 00 */
+#else
 	immr->im_siu_conf.sc_sdcr &= ~0x0f;	/* RAID = LAID = 0 */
 
 	/* set SHFT/CLOCK division factor 4
@@ -821,7 +842,21 @@ static void lcd_ctrl_init (void *lcdbase)
 	immr->im_clkrst.car_sccr &= ~0x1F;
 	immr->im_clkrst.car_sccr |= LCD_DF;	/* was 8 */
 
-#ifndef CONFIG_EDT32F10
+#endif /* CONFIG_RBC823 */
+
+#if defined(CONFIG_RBC823)
+	/* Enable LCD on port D.
+	 */
+	immr->im_ioport.iop_pddat &= 0x0300;
+	immr->im_ioport.iop_pdpar |= 0x1CFF;
+	immr->im_ioport.iop_pddir |= 0x1CFF;
+
+	/* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
+	 */
+	immr->im_cpm.cp_pbdat &= ~0x00005001;
+	immr->im_cpm.cp_pbpar &= ~0x00005001;
+	immr->im_cpm.cp_pbdir |=  0x00005001;
+#elif !defined(CONFIG_EDT32F10)
 	/* Enable LCD on port D.
 	 */
 	immr->im_ioport.iop_pdpar |= 0x1FFF;
@@ -850,18 +885,22 @@ static void lcd_ctrl_init (void *lcdbase)
 
 	/* MORE HACKS...This must be updated according to 823 manual
 	 * for different panels.
+	 * Udi Finkelstein - done - see below:
+	 * Note: You better not try unsupported combinations such as
+	 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
 	 */
-#ifndef CONFIG_EDT32F10
+	lchcr_hpc_tmp =
+	       	(panel_info.vl_col *
+		 (panel_info.vl_tft ? 8 :
+			(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
+			 /* use << to mult by: single scan = 1, dual scan = 2 */
+			  panel_info.vl_splt) *
+			 (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
+
 	lcdp->lcd_lchcr = LCHCR_BO |
 			  LCDBIT (LCHCR_AT_BIT, 4) |
-			  LCDBIT (LCHCR_HPC_BIT, panel_info.vl_col) |
+			  LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
 			  panel_info.vl_wbl;
-#else
-	lcdp->lcd_lchcr = LCHCR_BO |
-			  LCDBIT (LCHCR_AT_BIT, 4) |
-			  LCDBIT (LCHCR_HPC_BIT, panel_info.vl_col/4) |
-			  panel_info.vl_wbl;
-#endif
 
 	lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
 			  LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
@@ -975,13 +1014,18 @@ static void lcd_enable (void)
 	volatile lcd823_t *lcdp = &immr->im_lcd;
 
 	/* Enable the LCD panel */
+#ifndef CONFIG_RBC823
 	immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25));		/* LAM = 1 */
+#endif
 	lcdp->lcd_lccr |= LCCR_PON;
 
 #ifdef CONFIG_V37
 	/* Turn on display backlight */
 	immr->im_cpm.cp_pbpar |= 0x00008000;
 	immr->im_cpm.cp_pbdir |= 0x00008000;
+#elif defined(CONFIG_RBC823)
+	/* Turn on display backlight */
+	immr->im_cpm.cp_pbdat |= 0x00004000;
 #endif
 
 #if defined(CONFIG_LWMON)
@@ -1005,12 +1049,20 @@ static void lcd_enable (void)
 	r360_i2c_lcd_write(0x47, 0xFF);
     }
 #endif /* CONFIG_R360MPI */
+#ifdef CONFIG_RBC823
+	udelay(200000); /* wait 200ms */
+	/* Turn VEE_ON first */
+	immr->im_cpm.cp_pbdat |= 0x00000001;
+	udelay(200000); /* wait 200ms */
+	/* Now turn on LCD_ON */
+	immr->im_cpm.cp_pbdat |= 0x00001000;
+#endif
 }
 
 /*----------------------------------------------------------------------*/
 
-#ifdef	NOT_USED_SO_FAR
+#if defined (CONFIG_RBC823)
-static void lcd_disable (void)
+void lcd_disable (void)
 {
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile lcd823_t *lcdp = &immr->im_lcd;
@@ -1032,9 +1084,14 @@ static void lcd_disable (void)
 #endif /* CONFIG_LWMON */
 	/* Disable the LCD panel */
 	lcdp->lcd_lccr &= ~LCCR_PON;
+#ifdef CONFIG_RBC823
+	/* Turn off display backlight, VEE and LCD_ON */
+	immr->im_cpm.cp_pbdat &= ~0x00005001;
+#else
 	immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25));	/* LAM = 0 */
+#endif /* CONFIG_RBC823 */
 }
-#endif	/* NOT_USED_SO_FAR */
+#endif	/* NOT_USED_SO_FAR || CONFIG_RBC823 */
 
 
 /************************************************************************/

cpu/mpc8xx/start.S

@@ -723,7 +723,7 @@ trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
-	rlwinm	r9, r7, 0, 22, 31	/* _start & 0x3FF	*/
+	li	r9, 0x100		/* reset vector always at 0x100 */
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */

cpu/ppc4xx/start.S

@@ -1381,7 +1381,7 @@ trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 
-	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
+	li	r9, 0x100		/* reset vector always at 0x100 */
 
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */

drivers/Makefile

@@ -30,7 +30,8 @@ LIB	= libdrivers.a
 OBJS	= 3c589.o 5701rls.o ali512x.o at91rm9200_ether.o \
 	  bcm570x.o bcm570x_autoneg.o cfb_console.o \
 	  cs8900.o ct69000.o dc2114x.o          \
-	  eepro100.o i8042.o i82365.o inca-ip_sw.o \
+	  e1000.o eepro100.o \
+	  i8042.o i82365.o inca-ip_sw.o \
 	  lan91c96.o             natsemi.o \
 	  ns16550.o ns8382x.o ns87308.o \
 	  pci.o pci_auto.o pci_indirect.o \

include/commproc.h

@@ -1331,6 +1331,7 @@ typedef struct scc_enet {
 
 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
     defined(CONFIG_R360MPI) || \
+    defined(CONFIG_RBC823) || \
     defined(CONFIG_TQM823L) || \
     defined(CONFIG_TQM850L) || \
     defined(CONFIG_ETX094)  || \

include/configs/FADS823.h

@@ -58,7 +58,7 @@
 
 /* Wireless 56Khz 4PPM keyboard on SMCx */
 
-/*#define CONFIG_WL_4PPM_KEYBOARD		1 */
+/*#define CONFIG_KEYBOARD		1 */
 #define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/* SMC to use (0 indexed) */
 
 /*

include/configs/GENIETV.h

@@ -63,7 +63,7 @@
 
 /* Wireless 56Khz 4PPM keyboard on SMCx */
 
-/*#define CONFIG_WL_4PPM_KEYBOARD		0 */
+/*#define CONFIG_KEYBOARD		0 */
 /*#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/  SMC to use (0 indexed) */
 
 /*

include/configs/KUP4K.h

@@ -41,39 +41,41 @@
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600	/* console baudrate		*/
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
 #if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
 #else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 1 second	*/
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
 #endif
 
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
-#if 0
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-#endif
 
 #undef	CONFIG_BOOTARGS
 
-#define CONFIG_NFSBOOTCOMMAND \
-    "dhcp ;"\
-	"setenv bootargs root=/dev/nfs ro nfsroot=$(nfsip):$(rootpath) "\
-	"ip=$(ipaddr):$(nfsip):$(gatewayip):"\
-	"$(netmask):heydeck.eva:eth0:off; "\
-    "bootm 100000"
 
-#define CONFIG_RAMBOOTCOMMAND	\
+#define	CONFIG_EXTRA_ENV_SETTINGS					  \
-    "diskboot 100000 0:1; "\
+"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\
-    "setenv bootargs root=/dev/hda2 panic=1 "\
+ diskboot 200000 0:1; bootm 200000\0"                                     \
-	"ip=192.168.0.71:192.168.0.100:192.168.0.2:255.255.255.0; "\
+"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\
-    "bootm"
+ diskboot 200000 2:1; bootm 200000\0"                                     \
+"nfs_boot=dhcp; run nfsargs addip; bootm 200000\0"                        \
+"panic_boot=echo No Bootdevice !!! reset\0"                               \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath)\0" \
+"ramargs=setenv bootargs root=/dev/ram rw\0"			          \
+"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsip):$(gatewayip)\
+:$(netmask):$(hostname):$(netdev):off panic=1\0"                          \
+"netdev=eth0\0"                                                           \
+"load=tftp 200000 bootloader.bitmap;tftp 100000 u-boot.bin\0"             \
+"update=protect off 1:0-8;era 1:0-8;cp.b 100000 40000000 $(filesize);\
+cp.b 200000 40040000 14000\0"                                                   \
+"nfsip=192.168.2.19\0"
 
 #define CONFIG_BOOTCOMMAND  \
-    "run ramboot "\
+    "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
-    "run nfsboot"
+
 
 #define CONFIG_MISC_INIT_R  1
 
@@ -124,12 +126,14 @@
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CFG_LOAD_ADDR		0x200000	/* default load address	*/
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+#define CFG_CONSOLE_INFO_QUIET 1
+
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
@@ -250,7 +254,7 @@
  *
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
-#define CFG_PLPRCR ( (3-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -259,7 +263,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF00
-#define CFG_SCCR	( SCCR_TBS  |   SCCR_EBDF00 |  \
+#define CFG_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -428,12 +432,12 @@
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
 
-#if NOT_USED_FOR_NOW
+
 #define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
 #if 0
 #define CONFIG_AUTOBOOT_PROMPT		"Boote in %d Sekunden - stop mit \"2\"\n"
 #endif
-#define CONFIG_AUTOBOOT_STOP_STR	"2" /* easy to stop for now */
+#define CONFIG_AUTOBOOT_STOP_STR	"." /* easy to stop for now */
-#endif /* NOT_USED_FOR_NOW */
+
 
 #endif	/* __CONFIG_H */

include/configs/RBC823.h

@@ -0,0 +1,418 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Udi Finkelstein udif@udif.com
+ * For the RBC823 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_RBC823		1	/* ...on a RBC823 module	*/
+
+
+#if 0
+#define DEBUG			1
+#define CONFIG_LAST_STAGE_INIT
+#endif
+#define CONFIG_KEYBOARD		1	/* This board has a custom keybpard */
+#define CONFIG_LCD		1	/* use LCD controller ...	*/
+#define CONFIG_HITACHI_SP19X001_Z1A	/* The LCD type we use */
+
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_SMC1
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    48000000L
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef	CONFIG_RTC_MPC8xx		/* don't use internal RTC of MPC8xx (no battery)	*/
+
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 40000
+#define CFG_I2C_SLAVE 0xfe
+#define CFG_I2C_EEPROM_ADDR       0x50
+#define CFG_I2C_EEPROM_ADDR_LEN   1
+#define CFG_EEPROM_WRITE_BITS        4
+#define CFG_EEPROM_WRITE_DELAY_MS   10
+
+#define CONFIG_COMMANDS	      ( CFG_CMD_ALL	& \
+				~CFG_CMD_PCMCIA	& \
+				~CFG_CMD_IDE	& \
+				~CFG_CMD_PCI	& \
+				~CFG_CMD_FDC	& \
+				~CFG_CMD_HWFLOW	& \
+				~CFG_CMD_FDOS	& \
+				~CFG_CMD_SCSI	& \
+				~CFG_CMD_SETGETDCR	& \
+				~CFG_CMD_BSP	& \
+				~CFG_CMD_USB	& \
+				~CFG_CMD_VFD	& \
+				~CFG_CMD_SPI	& \
+				/* ~CFG_CMD_I2C	& */ \
+				~CFG_CMD_IRQ	& \
+				~CFG_CMD_NAND	& \
+				~CFG_CMD_JFFS2	& \
+				~CFG_CMD_DTT	& \
+				~CFG_CMD_MII	& \
+				/*~CFG_CMD_NET	&*/ \
+				/*~CFG_CMD_ELF	&*/ \
+				/* ~CFG_CMD_EEPROM	& */ \
+				~CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x0100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF00000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+/*
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+*/
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+/*
+ * for 48 MHz, we use a 4 MHz clock * 12
+ */
+#define CFG_PLPRCR							\
+		( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
+		         SCCR_PRQEN   | SCCR_EBDF00   | \
+		         SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
+			 SCCR_DFALCD00)
+
+#ifdef NOT_USED
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+#endif
+
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x04000000	/* D.O.C Millenium	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
+
+#define CFG_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
+		          BR_PS_8 | BR_V)
+
+/*
+ * BR4 and OR4 (SDRAM)
+ *
+ */
+#define SDRAM_BASE4_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/*
+ * SDRAM timing:
+ */
+#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM)
+
+#define CFG_OR4_PRELIM	(~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
+#define CFG_BR4_PRELIM	((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	187		/* start with divider for 48 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */

include/devices.h

@@ -102,8 +102,8 @@ int	drv_vfd_init (void);
 #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
 int	drv_video_init (void);
 #endif
-#ifdef CONFIG_WL_4PPM_KEYBOARD
+#ifdef CONFIG_KEYBOARD
-int	drv_wlkbd_init (void);
+int	drv_keyboard_init (void);
 #endif
 
 #endif	/* _DEVICES_H_ */

include/lcd.h

@@ -29,6 +29,12 @@
 #ifndef _LCD_H_
 #define _LCD_H_
 
+#if defined(CONFIG_RBC823)
+void	lcd_disable (void);
+#endif
+
+extern char lcd_is_enabled;
+
 /* Video functions */
 
 int	lcd_init	(void *lcdbase);

include/mpc8xx.h

@@ -40,8 +40,8 @@
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control Register				11-9
  */
-#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count	*/
+#define SYPCR_SWTC	0xFFFF0000	/* Software Watchdog Timer Count	*/
-#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing			*/
+#define SYPCR_BMT	0x0000FF00	/* Bus Monitor Timing			*/
 #define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
 #define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
 #define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
@@ -78,7 +78,7 @@
 #define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
 #define SIUMCR_MLRC01	0x00000400	/* - " -				*/
 #define SIUMCR_MLRC10	0x00000800	/* - " -				*/
-#define SIUMCR_MLRC11	0x00000c00	/* - " -				*/
+#define SIUMCR_MLRC11	0x00000C00	/* - " -				*/
 #define SIUMCR_AEME	0x00000200	/* Asynchro External Master		*/
 #define SIUMCR_SEME	0x00000100	/* Synchro External Master		*/
 #define SIUMCR_BSC	0x00000080	/* Byte Select Configuration		*/
@@ -120,7 +120,7 @@
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
  */
-#define PLPRCR_MF_MSK	0xfff00000	/* Multiplication factor bits		*/
+#define PLPRCR_MF_MSK	0xFFF00000	/* Multiplication factor bits		*/
 #define PLPRCR_MF_SHIFT 0x00000014	/* Multiplication factor shift value	*/
 #define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
 #define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
@@ -182,24 +182,24 @@
 /*-----------------------------------------------------------------------
  * BR - Memory Controler: Base Register					16-9
  */
-#define BR_BA_MSK	0xffff8000	/* Base Address Mask			*/
+#define BR_BA_MSK	0xFFFF8000	/* Base Address Mask			*/
 #define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
-#define BR_PS_MSK	0x00000c00	/* Port Size Mask			*/
+#define BR_PS_MSK	0x00000C00	/* Port Size Mask			*/
 #define BR_PS_32	0x00000000	/* 32 bit port size			*/
 #define BR_PS_16	0x00000800	/* 16 bit port size			*/
 #define BR_PS_8		0x00000400	/*  8 bit port size			*/
 #define BR_PARE		0x00000200	/* Parity Enable			*/
 #define BR_WP		0x00000100	/* Write Protect			*/
-#define BR_MS_MSK	0x000000c0	/* Machine Select Mask			*/
+#define BR_MS_MSK	0x000000C0	/* Machine Select Mask			*/
 #define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
 #define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
-#define BR_MS_UPMB	0x000000c0	/* U.P.M.B Machine Select		*/
+#define BR_MS_UPMB	0x000000C0	/* U.P.M.B Machine Select		*/
 #define BR_V		0x00000001	/* Bank Valid				*/
 
 /*-----------------------------------------------------------------------
  * OR - Memory Controler: Option Register				16-11
  */
-#define OR_AM_MSK	0xffff8000	/* Address Mask Mask			*/
+#define OR_AM_MSK	0xFFFF8000	/* Address Mask Mask			*/
 #define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
 #define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
 					/* Address Multiplex			*/
@@ -210,7 +210,7 @@
 #define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
 #define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
 #define OR_BI		0x00000100	/* Burst inhibit			*/
-#define OR_SCY_MSK	0x000000f0	/* Cycle Lenght in Clocks		*/
+#define OR_SCY_MSK	0x000000F0	/* Cycle Lenght in Clocks		*/
 #define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
 #define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
 #define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
@@ -221,12 +221,12 @@
 #define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
 #define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
 #define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
-#define OR_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states		*/
+#define OR_SCY_10_CLK	0x000000A0	/* 10 clock cycles wait states		*/
-#define OR_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states		*/
+#define OR_SCY_11_CLK	0x000000B0	/* 11 clock cycles wait states		*/
-#define OR_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states		*/
+#define OR_SCY_12_CLK	0x000000C0	/* 12 clock cycles wait states		*/
-#define OR_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states		*/
+#define OR_SCY_13_CLK	0x000000D0	/* 13 clock cycles wait states		*/
-#define OR_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states		*/
+#define OR_SCY_14_CLK	0x000000E0	/* 14 clock cycles wait states		*/
-#define OR_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states		*/
+#define OR_SCY_15_CLK	0x000000F0	/* 15 clock cycles wait states		*/
 #define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
 #define OR_TRLX		0x00000004	/* Timing Relaxed			*/
 #define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
@@ -235,7 +235,7 @@
 /*-----------------------------------------------------------------------
  * MPTPR - Memory Periodic Timer Prescaler Register			16-17
  */
-#define MPTPR_PTP_MSK	0xff00		/* Periodic Timers Prescaler Mask	*/
+#define MPTPR_PTP_MSK	0xFF00		/* Periodic Timers Prescaler Mask	*/
 #define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2			*/
 #define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4			*/
 #define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8			*/
@@ -265,7 +265,7 @@
 /*-----------------------------------------------------------------------
  * Machine A Mode Register						16-13
  */
-#define MAMR_PTA_MSK	0xff000000	/* Periodic Timer A period mask		*/
+#define MAMR_PTA_MSK	0xFF000000	/* Periodic Timer A period mask		*/
 #define MAMR_PTA_SHIFT	0x00000018	/* Periodic Timer A period shift	*/
 #define MAMR_PTAE	0x00800000	/* Periodic Timer A Enable		*/
 #define MAMR_AMA_MSK	0x00700000	/* Addess Multiplexing size A		*/
@@ -280,17 +280,17 @@
 #define MAMR_DSA_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
 #define MAMR_DSA_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
 #define MAMR_DSA_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
-#define MAMR_G0CLA_MSK	0x0000e000	/* General Line 0 Control A		*/
+#define MAMR_G0CLA_MSK	0x0000E000	/* General Line 0 Control A		*/
 #define MAMR_G0CLA_A12	0x00000000	/* General Line 0 : A12			*/
 #define MAMR_G0CLA_A11	0x00002000	/* General Line 0 : A11			*/
 #define MAMR_G0CLA_A10	0x00004000	/* General Line 0 : A10			*/
 #define MAMR_G0CLA_A9	0x00006000	/* General Line 0 : A9			*/
 #define MAMR_G0CLA_A8	0x00008000	/* General Line 0 : A8			*/
-#define MAMR_G0CLA_A7	0x0000a000	/* General Line 0 : A7			*/
+#define MAMR_G0CLA_A7	0x0000A000	/* General Line 0 : A7			*/
-#define MAMR_G0CLA_A6	0x0000c000	/* General Line 0 : A6			*/
+#define MAMR_G0CLA_A6	0x0000C000	/* General Line 0 : A6			*/
-#define MAMR_G0CLA_A5	0x0000e000	/* General Line 0 : A5			*/
+#define MAMR_G0CLA_A5	0x0000E000	/* General Line 0 : A5			*/
 #define MAMR_GPL_A4DIS	0x00001000	/* GPL_A4 ouput line Disable		*/
-#define MAMR_RLFA_MSK	0x00000f00	/* Read Loop Field A mask		*/
+#define MAMR_RLFA_MSK	0x00000F00	/* Read Loop Field A mask		*/
 #define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time	*/
 #define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times	*/
 #define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
@@ -300,14 +300,14 @@
 #define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
 #define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
 #define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
-#define MAMR_RLFA_10X	0x00000a00	/* The Read Loop is executed 10 times	*/
+#define MAMR_RLFA_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
-#define MAMR_RLFA_11X	0x00000b00	/* The Read Loop is executed 11 times	*/
+#define MAMR_RLFA_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
-#define MAMR_RLFA_12X	0x00000c00	/* The Read Loop is executed 12 times	*/
+#define MAMR_RLFA_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
-#define MAMR_RLFA_13X	0x00000d00	/* The Read Loop is executed 13 times	*/
+#define MAMR_RLFA_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
-#define MAMR_RLFA_14X	0x00000e00	/* The Read Loop is executed 14 times	*/
+#define MAMR_RLFA_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
-#define MAMR_RLFA_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
+#define MAMR_RLFA_15X	0x00000F00	/* The Read Loop is executed 15 times	*/
 #define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
-#define MAMR_WLFA_MSK	0x000000f0	/* Write Loop Field A mask		*/
+#define MAMR_WLFA_MSK	0x000000F0	/* Write Loop Field A mask		*/
 #define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time	*/
 #define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times	*/
 #define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times	*/
@@ -317,14 +317,14 @@
 #define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times	*/
 #define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times	*/
 #define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times	*/
-#define MAMR_WLFA_10X	0x000000a0	/* The Write Loop is executed 10 times	*/
+#define MAMR_WLFA_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
-#define MAMR_WLFA_11X	0x000000b0	/* The Write Loop is executed 11 times	*/
+#define MAMR_WLFA_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
-#define MAMR_WLFA_12X	0x000000c0	/* The Write Loop is executed 12 times	*/
+#define MAMR_WLFA_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
-#define MAMR_WLFA_13X	0x000000d0	/* The Write Loop is executed 13 times	*/
+#define MAMR_WLFA_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
-#define MAMR_WLFA_14X	0x000000e0	/* The Write Loop is executed 14 times	*/
+#define MAMR_WLFA_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
-#define MAMR_WLFA_15X	0x000000f0	/* The Write Loop is executed 15 times	*/
+#define MAMR_WLFA_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
 #define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times	*/
-#define MAMR_TLFA_MSK	0x0000000f	/* Timer Loop Field A mask		*/
+#define MAMR_TLFA_MSK	0x0000000F	/* Timer Loop Field A mask		*/
 #define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
 #define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
 #define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
@@ -334,18 +334,18 @@
 #define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
 #define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
 #define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
-#define MAMR_TLFA_10X	0x0000000a	/* The Timer Loop is executed 10 times	*/
+#define MAMR_TLFA_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
-#define MAMR_TLFA_11X	0x0000000b	/* The Timer Loop is executed 11 times	*/
+#define MAMR_TLFA_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
-#define MAMR_TLFA_12X	0x0000000c	/* The Timer Loop is executed 12 times	*/
+#define MAMR_TLFA_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
-#define MAMR_TLFA_13X	0x0000000d	/* The Timer Loop is executed 13 times	*/
+#define MAMR_TLFA_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
-#define MAMR_TLFA_14X	0x0000000e	/* The Timer Loop is executed 14 times	*/
+#define MAMR_TLFA_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
-#define MAMR_TLFA_15X	0x0000000f	/* The Timer Loop is executed 15 times	*/
+#define MAMR_TLFA_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
 #define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
 
 /*-----------------------------------------------------------------------
  * Machine B Mode Register						16-13
  */
-#define MAMR_PTB_MSK	0xff000000	/* Periodic Timer B period mask		*/
+#define MAMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
 #define MAMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
 #define MAMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
 #define MAMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
@@ -360,17 +360,17 @@
 #define MAMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
 #define MAMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
 #define MAMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
-#define MAMR_G0CLB_MSK	0x0000e000	/* General Line 0 Control B		*/
+#define MAMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
 #define MAMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
 #define MAMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
 #define MAMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
 #define MAMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
 #define MAMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
-#define MAMR_G0CLB_A7	0x0000a000	/* General Line 0 : A7			*/
+#define MAMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
-#define MAMR_G0CLB_A6	0x0000b000	/* General Line 0 : A6			*/
+#define MAMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
-#define MAMR_G0CLB_A5	0x0000e000	/* General Line 0 : A5			*/
+#define MAMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/
 #define MAMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
-#define MAMR_RLFB_MSK	0x00000f00	/* Read Loop Field B mask		*/
+#define MAMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
 #define MAMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
 #define MAMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
 #define MAMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
@@ -380,14 +380,14 @@
 #define MAMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
 #define MAMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
 #define MAMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
-#define MAMR_RLFB_10X	0x00000a00	/* The Read Loop is executed 10 times	*/
+#define MAMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
-#define MAMR_RLFB_11X	0x00000b00	/* The Read Loop is executed 11 times	*/
+#define MAMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
-#define MAMR_RLFB_12X	0x00000c00	/* The Read Loop is executed 12 times	*/
+#define MAMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
-#define MAMR_RLFB_13X	0x00000d00	/* The Read Loop is executed 13 times	*/
+#define MAMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
-#define MAMR_RLFB_14X	0x00000e00	/* The Read Loop is executed 14 times	*/
+#define MAMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
 #define MAMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
 #define MAMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
-#define MAMR_WLFB_MSK	0x000000f0	/* Write Loop Field B mask		*/
+#define MAMR_WLFB_MSK	0x000000F0	/* Write Loop Field B mask		*/
 #define MAMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
 #define MAMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
 #define MAMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
@@ -397,14 +397,14 @@
 #define MAMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
 #define MAMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
 #define MAMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
-#define MAMR_WLFB_10X	0x000000a0	/* The Write Loop is executed 10 times	*/
+#define MAMR_WLFB_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
-#define MAMR_WLFB_11X	0x000000b0	/* The Write Loop is executed 11 times	*/
+#define MAMR_WLFB_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
-#define MAMR_WLFB_12X	0x000000c0	/* The Write Loop is executed 12 times	*/
+#define MAMR_WLFB_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
-#define MAMR_WLFB_13X	0x000000d0	/* The Write Loop is executed 13 times	*/
+#define MAMR_WLFB_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
-#define MAMR_WLFB_14X	0x000000e0	/* The Write Loop is executed 14 times	*/
+#define MAMR_WLFB_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
-#define MAMR_WLFB_15X	0x000000f0	/* The Write Loop is executed 15 times	*/
+#define MAMR_WLFB_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
 #define MAMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
-#define MAMR_TLFB_MSK	0x0000000f	/* Timer Loop Field B mask		*/
+#define MAMR_TLFB_MSK	0x0000000F	/* Timer Loop Field B mask		*/
 #define MAMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
 #define MAMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
 #define MAMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
@@ -414,12 +414,12 @@
 #define MAMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
 #define MAMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
 #define MAMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
-#define MAMR_TLFB_10X	0x0000000a	/* The Timer Loop is executed 10 times	*/
+#define MAMR_TLFB_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
-#define MAMR_TLFB_11X	0x0000000b	/* The Timer Loop is executed 11 times	*/
+#define MAMR_TLFB_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
-#define MAMR_TLFB_12X	0x0000000c	/* The Timer Loop is executed 12 times	*/
+#define MAMR_TLFB_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
-#define MAMR_TLFB_13X	0x0000000d	/* The Timer Loop is executed 13 times	*/
+#define MAMR_TLFB_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
-#define MAMR_TLFB_14X	0x0000000e	/* The Timer Loop is executed 14 times	*/
+#define MAMR_TLFB_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
-#define MAMR_TLFB_15X	0x0000000f	/* The Timer Loop is executed 15 times	*/
+#define MAMR_TLFB_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
 #define MAMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
 
 /*-----------------------------------------------------------------------
@@ -446,13 +446,13 @@
 /*-----------------------------------------------------------------------
  * Timer Mode Register							18-9
  */
-#define TMR_PS_MSK              0xff00  /* Prescaler Value 			*/
+#define TMR_PS_MSK              0xFF00  /* Prescaler Value 			*/
 #define TMR_PS_SHIFT                 8  /* Prescaler position			*/
-#define TMR_CE_MSK              0x00c0  /* Capture Edge and Enable Interrupt	*/
+#define TMR_CE_MSK              0x00C0  /* Capture Edge and Enable Interrupt	*/
 #define TMR_CE_INTR_DIS         0x0000  /* Disable Interrupt on capture event 	*/
 #define TMR_CE_RISING           0x0040  /* Capture on Rising TINx edge only 	*/
 #define TMR_CE_FALLING          0x0080  /* Capture on Falling TINx edge only 	*/
-#define TMR_CE_ANY              0x00c0  /* Capture on any TINx edge 		*/
+#define TMR_CE_ANY              0x00C0  /* Capture on any TINx edge 		*/
 #define TMR_OM                  0x0020  /* Output Mode 				*/
 #define TMR_ORI                 0x0010  /* Output Reference Interrupt Enable	*/
 #define TMR_FRR                 0x0008  /* Free Run/Restart 			*/
@@ -505,7 +505,7 @@
 
 #define PCMCIA_VS1(slot)	(0x80000000 >> (slot << 4))
 #define PCMCIA_VS2(slot)	(0x40000000 >> (slot << 4))
-#define PCMCIA_VS_MASK(slot)	(0xc0000000 >> (slot << 4))
+#define PCMCIA_VS_MASK(slot)	(0xC0000000 >> (slot << 4))
 #define PCMCIA_VS_SHIFT(slot)	(30 - (slot << 4))
 
 #define PCMCIA_WP(slot)		(0x20000000 >> (slot << 4))

include/pci_ids.h

@@ -1367,6 +1367,19 @@
 #define PCI_DEVICE_ID_INTEL_82430	0x0486
 #define PCI_DEVICE_ID_INTEL_82434	0x04a3
 #define PCI_DEVICE_ID_INTEL_I960	0x0960
+#define PCI_DEVICE_ID_INTEL_82542       	0x1000
+#define PCI_DEVICE_ID_INTEL_82543GC_FIBER  	0x1001
+#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 	0x1004
+#define PCI_DEVICE_ID_INTEL_82544EI_COPPER 	0x1008
+#define PCI_DEVICE_ID_INTEL_82544EI_FIBER 	0x1009
+#define PCI_DEVICE_ID_INTEL_82544GC_COPPER 	0x100C
+#define PCI_DEVICE_ID_INTEL_82544GC_LOM   	0x100D
+#define PCI_DEVICE_ID_INTEL_82540EM		0x100E
+#define PCI_DEVICE_ID_INTEL_82545EM_COPPER	0x100F
+#define PCI_DEVICE_ID_INTEL_82546EB_COPPER	0x1010
+#define PCI_DEVICE_ID_INTEL_82545EM_FIBER	0x1011
+#define PCI_DEVICE_ID_INTEL_82546EB_FIBER	0x1012
+#define PCI_DEVICE_ID_INTEL_82540EM_LOM		0x1015
 #define PCI_DEVICE_ID_INTEL_82559	0x1030
 #define PCI_DEVICE_ID_INTEL_82559ER	0x1209
 #define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221

include/status_led.h

@@ -296,6 +296,25 @@ void status_led_set  (int led, int state);
 
 # define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
 
+/*****  RBC823    ********************************************************/
+#elif defined(CONFIG_RBC823)
+
+# define STATUS_LED_PAR         im_ioport.iop_pcpar
+# define STATUS_LED_DIR         im_ioport.iop_pcdir
+#  undef STATUS_LED_ODR
+# define STATUS_LED_DAT         im_ioport.iop_pcdat
+
+# define STATUS_LED_BIT         0x0002          /* LED 0 is on PC.14 */
+# define STATUS_LED_PERIOD      (CFG_HZ / 2)
+# define STATUS_LED_STATE       STATUS_LED_BLINKING
+# define STATUS_LED_BIT1        0x0004          /* LED 1 is on PC.13 */
+# define STATUS_LED_PERIOD1     (CFG_HZ)
+# define STATUS_LED_STATE1      STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE      1               /* LED on for bit == 1  */
+
+# define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
+
 /************************************************************************/
 #else
 # error Status LED configuration missing

lib_ppc/board.c

@@ -438,10 +438,10 @@ void board_init_f (ulong bootflag)
 
 	/*
 	 * reserve memory for U-Boot code, data & bss
-	 * round down to next 16 kB limit
+	 * round down to next 4 kB limit
 	 */
 	addr -= len;
-	addr &= ~(16 * 1024 - 1);
+	addr &= ~(4096 - 1);
 
 #ifdef DEBUG
 	printf ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);

net/bootp.c

@@ -55,7 +55,7 @@ ulong		seed1, seed2;
 
 #if (CONFIG_COMMANDS & CFG_CMD_DHCP)
 dhcp_state_t dhcp_state = INIT;
-unsigned int dhcp_leasetime = 0;
+unsigned long dhcp_leasetime = 0;
 IPaddr_t NetDHCPServerIP = 0;
 static void DhcpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len);
 
@@ -712,7 +712,7 @@ static void DhcpOptionsProcess(uchar *popt)
 				NetOurRootPath[size] = 0 ;
 				break;
 			case 51:
-				dhcp_leasetime = *(unsigned int *)(popt + 2);
+				NetCopyLong (&dhcp_leasetime, (ulong *)(popt + 2));
 				break;
 			case 53:		/* Ignore Message Type Option */
 				break;

net/eth.c

@@ -31,6 +31,7 @@
 extern int gt6426x_eth_initialize(bd_t *bis);
 #endif
 
+extern int e1000_initialize(bd_t*);
 extern int eepro100_initialize(bd_t*);
 extern int natsemi_initialize(bd_t*);
 extern int ns8382x_initialize(bd_t*);
@@ -103,6 +104,9 @@ int eth_initialize(bd_t *bis)
 #ifdef CONFIG_PLB2800_ETHER
 	plb2800_eth_initialize(bis);
 #endif
+#ifdef CONFIG_E1000
+	e1000_initialize(bis);
+#endif
 #ifdef CONFIG_EEPRO100
 	eepro100_initialize(bis);
 #endif