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ddr: marvell: update ddr controller init and freq

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Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham
2018-01-18 17:16:10 +13:00
committed by Stefan Roese
parent 8bddf678db
commit 672e559830
3 changed files with 34 additions and 21 deletions
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3
drivers/ddr/marvell/a38x/ddr3_topology_def.h
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@@ -70,7 +70,8 @@ enum speed_bin_table_elements {
SPEED_BIN_TWTR,
SPEED_BIN_TRTP,
SPEED_BIN_TWR,
SPEED_BIN_TMOD
SPEED_BIN_TMOD,
SPEED_BIN_TXPDLL
};
#endif /* _DDR3_TOPOLOGY_DEF_H */