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ram: stm32mp1: migrate trace to dev or log macro

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Define LOG_CATEGORY, use dev_ macro when it is possible
and migrate other trace to log_ macro.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrick Delaunay
2020-11-06 19:01:36 +01:00
committed by Patrick Delaunay
parent 997f7dab9d
commit 66b3b9db69
5 changed files with 117 additions and 104 deletions
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36
drivers/ram/stm32mp1/stm32mp1_ddr.c
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@@ -3,6 +3,8 @@
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#define LOG_CATEGORY UCLASS_RAM
#include <common.h>
#include <clk.h>
#include <log.h>
@@ -311,17 +313,17 @@ static void set_reg(const struct ddr_info *priv,
u32 base_addr = get_base_addr(priv, base);
const struct reg_desc *desc = ddr_registers[type].desc;
debug("init %s\n", ddr_registers[type].name);
log_debug("init %s\n", ddr_registers[type].name);
for (i = 0; i < ddr_registers[type].size; i++) {
ptr = (unsigned int *)(base_addr + desc[i].offset);
if (desc[i].par_offset == INVALID_OFFSET) {
pr_err("invalid parameter offset for %s", desc[i].name);
log_err("invalid parameter offset for %s", desc[i].name);
} else {
value = *((u32 *)((u32)param +
desc[i].par_offset));
writel(value, ptr);
debug("[0x%x] %s= 0x%08x\n",
(u32)ptr, desc[i].name, value);
log_debug("[0x%x] %s= 0x%08x\n",
(u32)ptr, desc[i].name, value);
}
}
}
@@ -564,16 +566,16 @@ static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
DDRPHYC_PGSR_RVERR |
DDRPHYC_PGSR_RVEIRR),
1000000);
debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
(u32)&phy->pgsr, pgsr, ret);
log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
(u32)&phy->pgsr, pgsr, ret);
}
void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
{
pir |= DDRPHYC_PIR_INIT;
writel(pir, &phy->pir);
debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
(u32)&phy->pir, pir, readl(&phy->pir));
log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
(u32)&phy->pir, pir, readl(&phy->pir));
/* need to wait 10 configuration clock before start polling */
udelay(10);
@@ -603,7 +605,7 @@ static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
panic("Timeout initialising DRAM : DDR->swstat = %x\n",
swstat);
debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
}
/* wait quasi dynamic register update */
@@ -634,7 +636,7 @@ static void wait_operating_mode(struct ddr_info *priv, int mode)
if (ret)
panic("Timeout DRAM : DDR->stat = %x\n", stat);
debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
}
void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
@@ -706,9 +708,9 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
panic("ddr power init failed\n");
start:
debug("name = %s\n", config->info.name);
debug("speed = %d kHz\n", config->info.speed);
debug("size = 0x%x\n", config->info.size);
log_debug("name = %s\n", config->info.name);
log_debug("speed = %d kHz\n", config->info.speed);
log_debug("size = 0x%x\n", config->info.size);
/*
* 1. Program the DWC_ddr_umctl2 registers
* 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
@@ -745,8 +747,8 @@ start:
/* 1.5. initialize registers ddr_umctl2 */
/* Stop uMCTL2 before PHY is ready */
clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
debug("[0x%08x] dfimisc = 0x%08x\n",
(u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
log_debug("[0x%08x] dfimisc = 0x%08x\n",
(u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
set_reg(priv, REG_REG, &config->c_reg);
set_reg(priv, REG_TIMING, &config->c_timing);
@@ -809,9 +811,9 @@ start:
wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
if (config->p_cal_present) {
debug("DDR DQS training skipped.\n");
log_debug("DDR DQS training skipped.\n");
} else {
debug("DDR DQS training : ");
log_debug("DDR DQS training : ");
/* 8. Disable Auto refresh and power down by setting
* - RFSHCTL3.dis_au_refresh = 1
* - PWRCTL.powerdown_en = 0